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@@ -2448,7 +2448,7 @@ static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
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* A value of 5us seems to be a good balance; safe for very low end
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* platforms but not overly aggressive on lower latency configs.
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*/
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-const static int latency_ns = 5000;
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+static const int latency_ns = 5000;
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static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
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{
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@@ -2559,7 +2559,7 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock,
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/* Calc sr entries for one plane configs */
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if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
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/* self-refresh has much higher latency */
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- const static int sr_latency_ns = 12000;
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+ static const int sr_latency_ns = 12000;
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sr_clock = planea_clock ? planea_clock : planeb_clock;
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line_time_us = ((sr_hdisplay * 1000) / sr_clock);
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@@ -2598,7 +2598,7 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
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/* Calc sr entries for one plane configs */
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if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
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/* self-refresh has much higher latency */
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- const static int sr_latency_ns = 12000;
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+ static const int sr_latency_ns = 12000;
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sr_clock = planea_clock ? planea_clock : planeb_clock;
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line_time_us = ((sr_hdisplay * 1000) / sr_clock);
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@@ -2667,7 +2667,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
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if (HAS_FW_BLC(dev) && sr_hdisplay &&
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(!planea_clock || !planeb_clock)) {
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/* self-refresh has much higher latency */
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- const static int sr_latency_ns = 6000;
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+ static const int sr_latency_ns = 6000;
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sr_clock = planea_clock ? planea_clock : planeb_clock;
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line_time_us = ((sr_hdisplay * 1000) / sr_clock);
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