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@@ -32,7 +32,7 @@
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#include <asm/blackfin.h>
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#include <asm/trace.h>
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-#if CONFIG_BFIN_KERNEL_CLOCK
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+#ifdef CONFIG_BFIN_KERNEL_CLOCK
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#include <asm/mach-common/clocks.h>
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#include <asm/mach/mem_init.h>
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#endif
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@@ -185,7 +185,7 @@ ENTRY(__start)
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/* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
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call _bf53x_relocate_l1_mem;
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-#if CONFIG_BFIN_KERNEL_CLOCK
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+#ifdef CONFIG_BFIN_KERNEL_CLOCK
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call _start_dma_code;
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#endif
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@@ -318,7 +318,7 @@ ENDPROC(_real_start)
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__FINIT
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.section .l1.text
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-#if CONFIG_BFIN_KERNEL_CLOCK
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+#ifdef CONFIG_BFIN_KERNEL_CLOCK
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ENTRY(_start_dma_code)
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/* Enable PHY CLK buffer output */
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@@ -398,12 +398,6 @@ ENTRY(_start_dma_code)
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w[p0] = r0.l;
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ssync;
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- p0.l = LO(EBIU_SDBCTL);
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- p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
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- r0 = mem_SDBCTL;
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- w[p0] = r0.l;
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- ssync;
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-
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P2.H = hi(EBIU_SDGCTL);
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P2.L = lo(EBIU_SDGCTL);
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R0 = [P2];
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