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@@ -180,6 +180,8 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
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/* Enable the PCH Receiver FDI PLL */
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rx_ctl_val = FDI_RX_PLL_ENABLE | FDI_RX_ENHANCE_FRAME_ENABLE |
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((intel_crtc->fdi_lanes - 1) << 19);
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+ if (dev_priv->fdi_rx_polarity_reversed)
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+ rx_ctl_val |= FDI_RX_POLARITY_REVERSED_LPT;
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I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
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POSTING_READ(_FDI_RXA_CTL);
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udelay(220);
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