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@@ -76,59 +76,59 @@ void rs690_pm_info(struct radeon_device *rdev)
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/* Get various system informations from bios */
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switch (crev) {
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case 1:
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- tmp.full = rfixed_const(100);
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- rdev->pm.igp_sideport_mclk.full = rfixed_const(info->info.ulBootUpMemoryClock);
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- rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
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- rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
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- rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->info.usFSBClock));
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- rdev->pm.igp_ht_link_width.full = rfixed_const(info->info.ucHTLinkWidth);
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+ tmp.full = dfixed_const(100);
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+ rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info.ulBootUpMemoryClock);
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+ rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
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+ rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
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+ rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
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+ rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
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break;
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case 2:
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- tmp.full = rfixed_const(100);
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- rdev->pm.igp_sideport_mclk.full = rfixed_const(info->info_v2.ulBootUpSidePortClock);
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- rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
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- rdev->pm.igp_system_mclk.full = rfixed_const(info->info_v2.ulBootUpUMAClock);
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- rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
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- rdev->pm.igp_ht_link_clk.full = rfixed_const(info->info_v2.ulHTLinkFreq);
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- rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp);
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- rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
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+ tmp.full = dfixed_const(100);
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+ rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info_v2.ulBootUpSidePortClock);
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+ rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
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+ rdev->pm.igp_system_mclk.full = dfixed_const(info->info_v2.ulBootUpUMAClock);
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+ rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
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+ rdev->pm.igp_ht_link_clk.full = dfixed_const(info->info_v2.ulHTLinkFreq);
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+ rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
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+ rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
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break;
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default:
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- tmp.full = rfixed_const(100);
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+ tmp.full = dfixed_const(100);
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/* We assume the slower possible clock ie worst case */
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/* DDR 333Mhz */
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- rdev->pm.igp_sideport_mclk.full = rfixed_const(333);
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+ rdev->pm.igp_sideport_mclk.full = dfixed_const(333);
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/* FIXME: system clock ? */
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- rdev->pm.igp_system_mclk.full = rfixed_const(100);
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- rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
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- rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
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- rdev->pm.igp_ht_link_width.full = rfixed_const(8);
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+ rdev->pm.igp_system_mclk.full = dfixed_const(100);
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+ rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
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+ rdev->pm.igp_ht_link_clk.full = dfixed_const(200);
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+ rdev->pm.igp_ht_link_width.full = dfixed_const(8);
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DRM_ERROR("No integrated system info for your GPU, using safe default\n");
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break;
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}
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} else {
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- tmp.full = rfixed_const(100);
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+ tmp.full = dfixed_const(100);
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/* We assume the slower possible clock ie worst case */
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/* DDR 333Mhz */
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- rdev->pm.igp_sideport_mclk.full = rfixed_const(333);
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+ rdev->pm.igp_sideport_mclk.full = dfixed_const(333);
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/* FIXME: system clock ? */
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- rdev->pm.igp_system_mclk.full = rfixed_const(100);
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- rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
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- rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
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- rdev->pm.igp_ht_link_width.full = rfixed_const(8);
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+ rdev->pm.igp_system_mclk.full = dfixed_const(100);
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+ rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
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+ rdev->pm.igp_ht_link_clk.full = dfixed_const(200);
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+ rdev->pm.igp_ht_link_width.full = dfixed_const(8);
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DRM_ERROR("No integrated system info for your GPU, using safe default\n");
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}
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/* Compute various bandwidth */
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/* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
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- tmp.full = rfixed_const(4);
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- rdev->pm.k8_bandwidth.full = rfixed_mul(rdev->pm.igp_system_mclk, tmp);
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+ tmp.full = dfixed_const(4);
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+ rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
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/* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
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* = ht_clk * ht_width / 5
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*/
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- tmp.full = rfixed_const(5);
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- rdev->pm.ht_bandwidth.full = rfixed_mul(rdev->pm.igp_ht_link_clk,
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+ tmp.full = dfixed_const(5);
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+ rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
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rdev->pm.igp_ht_link_width);
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- rdev->pm.ht_bandwidth.full = rfixed_div(rdev->pm.ht_bandwidth, tmp);
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+ rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
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if (tmp.full < rdev->pm.max_bandwidth.full) {
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/* HT link is a limiting factor */
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rdev->pm.max_bandwidth.full = tmp.full;
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@@ -136,10 +136,10 @@ void rs690_pm_info(struct radeon_device *rdev)
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/* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
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* = (sideport_clk * 14) / 10
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*/
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- tmp.full = rfixed_const(14);
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- rdev->pm.sideport_bandwidth.full = rfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
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- tmp.full = rfixed_const(10);
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- rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp);
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+ tmp.full = dfixed_const(14);
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+ rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
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+ tmp.full = dfixed_const(10);
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+ rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
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}
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void rs690_mc_init(struct radeon_device *rdev)
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@@ -239,20 +239,20 @@ void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
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return;
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}
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- if (crtc->vsc.full > rfixed_const(2))
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- wm->num_line_pair.full = rfixed_const(2);
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+ if (crtc->vsc.full > dfixed_const(2))
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+ wm->num_line_pair.full = dfixed_const(2);
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else
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- wm->num_line_pair.full = rfixed_const(1);
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-
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- b.full = rfixed_const(mode->crtc_hdisplay);
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- c.full = rfixed_const(256);
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- a.full = rfixed_div(b, c);
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- request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
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- request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
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- if (a.full < rfixed_const(4)) {
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+ wm->num_line_pair.full = dfixed_const(1);
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+
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+ b.full = dfixed_const(mode->crtc_hdisplay);
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+ c.full = dfixed_const(256);
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+ a.full = dfixed_div(b, c);
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+ request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
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+ request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
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+ if (a.full < dfixed_const(4)) {
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wm->lb_request_fifo_depth = 4;
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} else {
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- wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
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+ wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
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}
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/* Determine consumption rate
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@@ -261,23 +261,23 @@ void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
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* vsc = vertical scaling ratio, defined as source/destination
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* hsc = horizontal scaling ration, defined as source/destination
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*/
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- a.full = rfixed_const(mode->clock);
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- b.full = rfixed_const(1000);
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- a.full = rfixed_div(a, b);
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- pclk.full = rfixed_div(b, a);
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+ a.full = dfixed_const(mode->clock);
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+ b.full = dfixed_const(1000);
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+ a.full = dfixed_div(a, b);
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+ pclk.full = dfixed_div(b, a);
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if (crtc->rmx_type != RMX_OFF) {
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- b.full = rfixed_const(2);
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+ b.full = dfixed_const(2);
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if (crtc->vsc.full > b.full)
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b.full = crtc->vsc.full;
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- b.full = rfixed_mul(b, crtc->hsc);
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- c.full = rfixed_const(2);
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- b.full = rfixed_div(b, c);
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- consumption_time.full = rfixed_div(pclk, b);
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+ b.full = dfixed_mul(b, crtc->hsc);
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+ c.full = dfixed_const(2);
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+ b.full = dfixed_div(b, c);
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+ consumption_time.full = dfixed_div(pclk, b);
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} else {
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consumption_time.full = pclk.full;
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}
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- a.full = rfixed_const(1);
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- wm->consumption_rate.full = rfixed_div(a, consumption_time);
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+ a.full = dfixed_const(1);
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+ wm->consumption_rate.full = dfixed_div(a, consumption_time);
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/* Determine line time
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@@ -285,18 +285,18 @@ void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
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* LineTime = total number of horizontal pixels
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* pclk = pixel clock period(ns)
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*/
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- a.full = rfixed_const(crtc->base.mode.crtc_htotal);
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- line_time.full = rfixed_mul(a, pclk);
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+ a.full = dfixed_const(crtc->base.mode.crtc_htotal);
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+ line_time.full = dfixed_mul(a, pclk);
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/* Determine active time
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* ActiveTime = time of active region of display within one line,
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* hactive = total number of horizontal active pixels
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* htotal = total number of horizontal pixels
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*/
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- a.full = rfixed_const(crtc->base.mode.crtc_htotal);
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- b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
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- wm->active_time.full = rfixed_mul(line_time, b);
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- wm->active_time.full = rfixed_div(wm->active_time, a);
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+ a.full = dfixed_const(crtc->base.mode.crtc_htotal);
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+ b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
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+ wm->active_time.full = dfixed_mul(line_time, b);
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+ wm->active_time.full = dfixed_div(wm->active_time, a);
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/* Maximun bandwidth is the minimun bandwidth of all component */
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rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
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@@ -304,8 +304,8 @@ void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
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if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
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rdev->pm.sideport_bandwidth.full)
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rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
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- read_delay_latency.full = rfixed_const(370 * 800 * 1000);
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- read_delay_latency.full = rfixed_div(read_delay_latency,
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+ read_delay_latency.full = dfixed_const(370 * 800 * 1000);
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+ read_delay_latency.full = dfixed_div(read_delay_latency,
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rdev->pm.igp_sideport_mclk);
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} else {
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if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
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@@ -314,23 +314,23 @@ void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
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if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
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rdev->pm.ht_bandwidth.full)
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rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
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- read_delay_latency.full = rfixed_const(5000);
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+ read_delay_latency.full = dfixed_const(5000);
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}
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/* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
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- a.full = rfixed_const(16);
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- rdev->pm.sclk.full = rfixed_mul(rdev->pm.max_bandwidth, a);
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- a.full = rfixed_const(1000);
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- rdev->pm.sclk.full = rfixed_div(a, rdev->pm.sclk);
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+ a.full = dfixed_const(16);
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+ rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a);
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+ a.full = dfixed_const(1000);
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+ rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk);
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/* Determine chunk time
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* ChunkTime = the time it takes the DCP to send one chunk of data
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* to the LB which consists of pipeline delay and inter chunk gap
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* sclk = system clock(ns)
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*/
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- a.full = rfixed_const(256 * 13);
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- chunk_time.full = rfixed_mul(rdev->pm.sclk, a);
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- a.full = rfixed_const(10);
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- chunk_time.full = rfixed_div(chunk_time, a);
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+ a.full = dfixed_const(256 * 13);
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+ chunk_time.full = dfixed_mul(rdev->pm.sclk, a);
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+ a.full = dfixed_const(10);
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+ chunk_time.full = dfixed_div(chunk_time, a);
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/* Determine the worst case latency
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* NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
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@@ -340,13 +340,13 @@ void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
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* ChunkTime = time it takes the DCP to send one chunk of data to the LB
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* which consists of pipeline delay and inter chunk gap
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*/
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- if (rfixed_trunc(wm->num_line_pair) > 1) {
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- a.full = rfixed_const(3);
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- wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
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+ if (dfixed_trunc(wm->num_line_pair) > 1) {
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+ a.full = dfixed_const(3);
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+ wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
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wm->worst_case_latency.full += read_delay_latency.full;
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} else {
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- a.full = rfixed_const(2);
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- wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
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+ a.full = dfixed_const(2);
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+ wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
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wm->worst_case_latency.full += read_delay_latency.full;
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}
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@@ -360,34 +360,34 @@ void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
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* of data to the LB which consists of
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* pipeline delay and inter chunk gap
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*/
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- if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
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+ if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
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tolerable_latency.full = line_time.full;
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} else {
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- tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
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+ tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
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tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
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- tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
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+ tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
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tolerable_latency.full = line_time.full - tolerable_latency.full;
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}
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/* We assume worst case 32bits (4 bytes) */
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- wm->dbpp.full = rfixed_const(4 * 8);
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+ wm->dbpp.full = dfixed_const(4 * 8);
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/* Determine the maximum priority mark
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* width = viewport width in pixels
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*/
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- a.full = rfixed_const(16);
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- wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
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- wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
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- wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
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+ a.full = dfixed_const(16);
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+ wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
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+ wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
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|
|
+ wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
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|
|
|
|
/* Determine estimated width */
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|
estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
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|
|
- estimated_width.full = rfixed_div(estimated_width, consumption_time);
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|
- if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
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|
- wm->priority_mark.full = rfixed_const(10);
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|
+ estimated_width.full = dfixed_div(estimated_width, consumption_time);
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|
|
+ if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
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|
|
+ wm->priority_mark.full = dfixed_const(10);
|
|
|
} else {
|
|
|
- a.full = rfixed_const(16);
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|
|
- wm->priority_mark.full = rfixed_div(estimated_width, a);
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|
|
- wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
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|
|
+ a.full = dfixed_const(16);
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|
|
+ wm->priority_mark.full = dfixed_div(estimated_width, a);
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|
|
+ wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
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|
|
wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
|
|
|
}
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|
|
}
|
|
@@ -439,58 +439,58 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
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WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
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|
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if (mode0 && mode1) {
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- if (rfixed_trunc(wm0.dbpp) > 64)
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- a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
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+ if (dfixed_trunc(wm0.dbpp) > 64)
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+ a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
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else
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a.full = wm0.num_line_pair.full;
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- if (rfixed_trunc(wm1.dbpp) > 64)
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- b.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
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+ if (dfixed_trunc(wm1.dbpp) > 64)
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+ b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
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else
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b.full = wm1.num_line_pair.full;
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a.full += b.full;
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- fill_rate.full = rfixed_div(wm0.sclk, a);
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+ fill_rate.full = dfixed_div(wm0.sclk, a);
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if (wm0.consumption_rate.full > fill_rate.full) {
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b.full = wm0.consumption_rate.full - fill_rate.full;
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- b.full = rfixed_mul(b, wm0.active_time);
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- a.full = rfixed_mul(wm0.worst_case_latency,
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+ b.full = dfixed_mul(b, wm0.active_time);
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|
+ a.full = dfixed_mul(wm0.worst_case_latency,
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|
wm0.consumption_rate);
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a.full = a.full + b.full;
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- b.full = rfixed_const(16 * 1000);
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- priority_mark02.full = rfixed_div(a, b);
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+ b.full = dfixed_const(16 * 1000);
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+ priority_mark02.full = dfixed_div(a, b);
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|
} else {
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|
|
- a.full = rfixed_mul(wm0.worst_case_latency,
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|
+ a.full = dfixed_mul(wm0.worst_case_latency,
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|
|
wm0.consumption_rate);
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|
|
- b.full = rfixed_const(16 * 1000);
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- priority_mark02.full = rfixed_div(a, b);
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+ b.full = dfixed_const(16 * 1000);
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|
+ priority_mark02.full = dfixed_div(a, b);
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|
}
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|
|
if (wm1.consumption_rate.full > fill_rate.full) {
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|
b.full = wm1.consumption_rate.full - fill_rate.full;
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|
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- b.full = rfixed_mul(b, wm1.active_time);
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|
|
- a.full = rfixed_mul(wm1.worst_case_latency,
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|
|
+ b.full = dfixed_mul(b, wm1.active_time);
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|
|
+ a.full = dfixed_mul(wm1.worst_case_latency,
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|
|
wm1.consumption_rate);
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|
|
a.full = a.full + b.full;
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- b.full = rfixed_const(16 * 1000);
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|
|
- priority_mark12.full = rfixed_div(a, b);
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|
|
+ b.full = dfixed_const(16 * 1000);
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|
|
+ priority_mark12.full = dfixed_div(a, b);
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|
|
} else {
|
|
|
- a.full = rfixed_mul(wm1.worst_case_latency,
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|
|
+ a.full = dfixed_mul(wm1.worst_case_latency,
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|
|
wm1.consumption_rate);
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|
|
- b.full = rfixed_const(16 * 1000);
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|
|
- priority_mark12.full = rfixed_div(a, b);
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|
|
+ b.full = dfixed_const(16 * 1000);
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|
|
+ priority_mark12.full = dfixed_div(a, b);
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|
|
}
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|
|
if (wm0.priority_mark.full > priority_mark02.full)
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|
|
priority_mark02.full = wm0.priority_mark.full;
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|
|
- if (rfixed_trunc(priority_mark02) < 0)
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|
|
+ if (dfixed_trunc(priority_mark02) < 0)
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|
|
priority_mark02.full = 0;
|
|
|
if (wm0.priority_mark_max.full > priority_mark02.full)
|
|
|
priority_mark02.full = wm0.priority_mark_max.full;
|
|
|
if (wm1.priority_mark.full > priority_mark12.full)
|
|
|
priority_mark12.full = wm1.priority_mark.full;
|
|
|
- if (rfixed_trunc(priority_mark12) < 0)
|
|
|
+ if (dfixed_trunc(priority_mark12) < 0)
|
|
|
priority_mark12.full = 0;
|
|
|
if (wm1.priority_mark_max.full > priority_mark12.full)
|
|
|
priority_mark12.full = wm1.priority_mark_max.full;
|
|
|
- d1mode_priority_a_cnt = rfixed_trunc(priority_mark02);
|
|
|
- d2mode_priority_a_cnt = rfixed_trunc(priority_mark12);
|
|
|
+ d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
|
|
|
+ d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
|
|
|
if (rdev->disp_priority == 2) {
|
|
|
d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
|
|
|
d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
|
|
@@ -500,32 +500,32 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
|
|
|
WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
|
|
|
WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
|
|
|
} else if (mode0) {
|
|
|
- if (rfixed_trunc(wm0.dbpp) > 64)
|
|
|
- a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
|
|
|
+ if (dfixed_trunc(wm0.dbpp) > 64)
|
|
|
+ a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
|
|
|
else
|
|
|
a.full = wm0.num_line_pair.full;
|
|
|
- fill_rate.full = rfixed_div(wm0.sclk, a);
|
|
|
+ fill_rate.full = dfixed_div(wm0.sclk, a);
|
|
|
if (wm0.consumption_rate.full > fill_rate.full) {
|
|
|
b.full = wm0.consumption_rate.full - fill_rate.full;
|
|
|
- b.full = rfixed_mul(b, wm0.active_time);
|
|
|
- a.full = rfixed_mul(wm0.worst_case_latency,
|
|
|
+ b.full = dfixed_mul(b, wm0.active_time);
|
|
|
+ a.full = dfixed_mul(wm0.worst_case_latency,
|
|
|
wm0.consumption_rate);
|
|
|
a.full = a.full + b.full;
|
|
|
- b.full = rfixed_const(16 * 1000);
|
|
|
- priority_mark02.full = rfixed_div(a, b);
|
|
|
+ b.full = dfixed_const(16 * 1000);
|
|
|
+ priority_mark02.full = dfixed_div(a, b);
|
|
|
} else {
|
|
|
- a.full = rfixed_mul(wm0.worst_case_latency,
|
|
|
+ a.full = dfixed_mul(wm0.worst_case_latency,
|
|
|
wm0.consumption_rate);
|
|
|
- b.full = rfixed_const(16 * 1000);
|
|
|
- priority_mark02.full = rfixed_div(a, b);
|
|
|
+ b.full = dfixed_const(16 * 1000);
|
|
|
+ priority_mark02.full = dfixed_div(a, b);
|
|
|
}
|
|
|
if (wm0.priority_mark.full > priority_mark02.full)
|
|
|
priority_mark02.full = wm0.priority_mark.full;
|
|
|
- if (rfixed_trunc(priority_mark02) < 0)
|
|
|
+ if (dfixed_trunc(priority_mark02) < 0)
|
|
|
priority_mark02.full = 0;
|
|
|
if (wm0.priority_mark_max.full > priority_mark02.full)
|
|
|
priority_mark02.full = wm0.priority_mark_max.full;
|
|
|
- d1mode_priority_a_cnt = rfixed_trunc(priority_mark02);
|
|
|
+ d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
|
|
|
if (rdev->disp_priority == 2)
|
|
|
d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
|
|
|
WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
|
|
@@ -535,32 +535,32 @@ void rs690_bandwidth_update(struct radeon_device *rdev)
|
|
|
WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
|
|
|
S_006D4C_D2MODE_PRIORITY_B_OFF(1));
|
|
|
} else {
|
|
|
- if (rfixed_trunc(wm1.dbpp) > 64)
|
|
|
- a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
|
|
|
+ if (dfixed_trunc(wm1.dbpp) > 64)
|
|
|
+ a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
|
|
|
else
|
|
|
a.full = wm1.num_line_pair.full;
|
|
|
- fill_rate.full = rfixed_div(wm1.sclk, a);
|
|
|
+ fill_rate.full = dfixed_div(wm1.sclk, a);
|
|
|
if (wm1.consumption_rate.full > fill_rate.full) {
|
|
|
b.full = wm1.consumption_rate.full - fill_rate.full;
|
|
|
- b.full = rfixed_mul(b, wm1.active_time);
|
|
|
- a.full = rfixed_mul(wm1.worst_case_latency,
|
|
|
+ b.full = dfixed_mul(b, wm1.active_time);
|
|
|
+ a.full = dfixed_mul(wm1.worst_case_latency,
|
|
|
wm1.consumption_rate);
|
|
|
a.full = a.full + b.full;
|
|
|
- b.full = rfixed_const(16 * 1000);
|
|
|
- priority_mark12.full = rfixed_div(a, b);
|
|
|
+ b.full = dfixed_const(16 * 1000);
|
|
|
+ priority_mark12.full = dfixed_div(a, b);
|
|
|
} else {
|
|
|
- a.full = rfixed_mul(wm1.worst_case_latency,
|
|
|
+ a.full = dfixed_mul(wm1.worst_case_latency,
|
|
|
wm1.consumption_rate);
|
|
|
- b.full = rfixed_const(16 * 1000);
|
|
|
- priority_mark12.full = rfixed_div(a, b);
|
|
|
+ b.full = dfixed_const(16 * 1000);
|
|
|
+ priority_mark12.full = dfixed_div(a, b);
|
|
|
}
|
|
|
if (wm1.priority_mark.full > priority_mark12.full)
|
|
|
priority_mark12.full = wm1.priority_mark.full;
|
|
|
- if (rfixed_trunc(priority_mark12) < 0)
|
|
|
+ if (dfixed_trunc(priority_mark12) < 0)
|
|
|
priority_mark12.full = 0;
|
|
|
if (wm1.priority_mark_max.full > priority_mark12.full)
|
|
|
priority_mark12.full = wm1.priority_mark_max.full;
|
|
|
- d2mode_priority_a_cnt = rfixed_trunc(priority_mark12);
|
|
|
+ d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
|
|
|
if (rdev->disp_priority == 2)
|
|
|
d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
|
|
|
WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
|