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@@ -1643,11 +1643,15 @@ wlc_lcnphy_set_chanspec_tweaks(struct brcms_phy *pi, u16 chanspec)
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if (channel == 1 || channel == 2 || channel == 3 ||
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channel == 4 || channel == 9 ||
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channel == 10 || channel == 11 || channel == 12) {
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- si_pmu_pllcontrol(pi->sh->sih, 0x2, 0xffffffff, 0x03000c04);
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- si_pmu_pllcontrol(pi->sh->sih, 0x3, 0xffffff, 0x0);
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- si_pmu_pllcontrol(pi->sh->sih, 0x4, 0xffffffff, 0x200005c0);
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-
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- si_pmu_pllupd(pi->sh->sih);
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+ bcma_chipco_pll_write(&pi->d11core->bus->drv_cc, 0x2,
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+ 0x03000c04);
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+ bcma_chipco_pll_maskset(&pi->d11core->bus->drv_cc, 0x3,
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+ ~0x00ffffff, 0x0);
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+ bcma_chipco_pll_write(&pi->d11core->bus->drv_cc, 0x4,
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+ 0x200005c0);
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+
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+ bcma_cc_set32(&pi->d11core->bus->drv_cc, BCMA_CC_PMU_CTL,
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+ BCMA_CC_PMU_CTL_PLL_UPD);
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write_phy_reg(pi, 0x942, 0);
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wlc_lcnphy_txrx_spur_avoidance_mode(pi, false);
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pi_lcn->lcnphy_spurmod = false;
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@@ -1655,11 +1659,15 @@ wlc_lcnphy_set_chanspec_tweaks(struct brcms_phy *pi, u16 chanspec)
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write_phy_reg(pi, 0x425, 0x5907);
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} else {
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- si_pmu_pllcontrol(pi->sh->sih, 0x2, 0xffffffff, 0x03140c04);
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- si_pmu_pllcontrol(pi->sh->sih, 0x3, 0xffffff, 0x333333);
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- si_pmu_pllcontrol(pi->sh->sih, 0x4, 0xffffffff, 0x202c2820);
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-
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- si_pmu_pllupd(pi->sh->sih);
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+ bcma_chipco_pll_write(&pi->d11core->bus->drv_cc, 0x2,
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+ 0x03140c04);
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+ bcma_chipco_pll_maskset(&pi->d11core->bus->drv_cc, 0x3,
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+ ~0x00ffffff, 0x333333);
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+ bcma_chipco_pll_write(&pi->d11core->bus->drv_cc, 0x4,
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+ 0x202c2820);
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+
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+ bcma_cc_set32(&pi->d11core->bus->drv_cc, BCMA_CC_PMU_CTL,
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+ BCMA_CC_PMU_CTL_PLL_UPD);
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write_phy_reg(pi, 0x942, 0);
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wlc_lcnphy_txrx_spur_avoidance_mode(pi, true);
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@@ -4864,9 +4872,10 @@ void wlc_phy_init_lcnphy(struct brcms_phy *pi)
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wlc_phy_chanspec_set((struct brcms_phy_pub *) pi, pi->radio_chanspec);
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- si_pmu_regcontrol(pi->sh->sih, 0, 0xf, 0x9);
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+ bcma_chipco_regctl_maskset(&pi->d11core->bus->drv_cc, 0, ~0xf, 0x9);
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- si_pmu_chipcontrol(pi->sh->sih, 0, 0xffffffff, 0x03CDDDDD);
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+ bcma_chipco_chipctl_maskset(&pi->d11core->bus->drv_cc, 0, 0x0,
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+ 0x03CDDDDD);
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if ((pi->sh->boardflags & BFL_FEM)
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&& wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
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@@ -5078,7 +5087,7 @@ bool wlc_phy_attach_lcnphy(struct brcms_phy *pi)
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pi->hwpwrctrl_capable = true;
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}
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- pi->xtalfreq = si_pmu_alp_clock(pi->sh->sih);
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+ pi->xtalfreq = bcma_chipco_get_alp_clock(&pi->d11core->bus->drv_cc);
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pi_lcn->lcnphy_papd_rxGnCtrl_init = 0;
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pi->pi_fptr.init = wlc_phy_init_lcnphy;
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