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@@ -683,7 +683,10 @@ si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, u8 spuravoid)
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case BCM43236_CHIP_ID:
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case BCM43238_CHIP_ID:
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- /* BCM5357 needs to touch PLL1_PLLCTL[02], so offset PLL0_PLLCTL[02] by 6 */
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+ /*
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+ * BCM5357 needs to touch PLL1_PLLCTL[02],
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+ * so offset PLL0_PLLCTL[02] by 6
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+ */
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phypll_offset = (sih->chip == BCM5357_CHIP_ID) ? 6 : 0;
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/* RMW only the P1 divider */
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@@ -821,10 +824,12 @@ si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, u8 spuravoid)
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
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W_REG(&cc->pllcontrol_data, 0x88888854);
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- if (spuravoid == 1) { /* spur_avoid ON, enable 41/82/164Mhz clock mode */
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+ if (spuravoid == 1) {
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+ /* spur_avoid ON, so enable 41/82/164Mhz clock mode */
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
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W_REG(&cc->pllcontrol_data, 0x05201828);
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- } else { /* enable 40/80/160Mhz clock mode */
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+ } else {
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+ /* enable 40/80/160Mhz clock mode */
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
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W_REG(&cc->pllcontrol_data, 0x05001828);
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}
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@@ -847,11 +852,10 @@ si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, u8 spuravoid)
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W_REG(&cc->pllcontrol_data, 0x88888825);
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W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
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- if (spuravoid == 1) {
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+ if (spuravoid == 1)
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W_REG(&cc->pllcontrol_data, 0x00EC4EC4);
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- } else {
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+ else
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W_REG(&cc->pllcontrol_data, 0x00762762);
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- }
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tmp = PCTL_PLL_PLLCTL_UPD;
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break;
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