|
@@ -77,7 +77,7 @@
|
|
#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
|
|
#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
|
|
#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
|
|
#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
|
|
/* 14 free */
|
|
/* 14 free */
|
|
-#define X86_FEATURE_SYNC_RDTSC (3*32+15) /* RDTSC synchronizes the CPU */
|
|
|
|
|
|
+/* 15 free */
|
|
#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */
|
|
#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */
|
|
#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
|
|
#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
|
|
#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */
|
|
#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */
|