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@@ -512,11 +512,11 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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/* synchronise with the rendering channel, if necessary */
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if (likely(chan)) {
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- ret = RING_SPACE(chan, 10);
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- if (ret)
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- return ret;
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-
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if (nv_mclass(chan->object) < NV84_CHANNEL_IND_CLASS) {
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+ ret = RING_SPACE(chan, 8);
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+ if (ret)
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+ return ret;
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+
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
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OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
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OUT_RING (chan, sync->sem.offset);
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@@ -525,13 +525,17 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
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OUT_RING (chan, sync->sem.offset ^ 0x10);
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OUT_RING (chan, 0x74b1e000);
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- BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
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- OUT_RING (chan, NvSema);
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} else
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if (nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) {
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u64 offset = nv84_fence_crtc(chan, nv_crtc->index);
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offset += sync->sem.offset;
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+ ret = RING_SPACE(chan, 12);
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+ if (ret)
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+ return ret;
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+
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+ BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
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+ OUT_RING (chan, chan->vram);
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BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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OUT_RING (chan, upper_32_bits(offset));
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OUT_RING (chan, lower_32_bits(offset));
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@@ -546,6 +550,10 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
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u64 offset = nv84_fence_crtc(chan, nv_crtc->index);
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offset += sync->sem.offset;
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+ ret = RING_SPACE(chan, 10);
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+ if (ret)
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+ return ret;
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+
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BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
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OUT_RING (chan, upper_32_bits(offset));
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OUT_RING (chan, lower_32_bits(offset));
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