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@@ -74,11 +74,9 @@
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#define FLAGS_CBC BIT(1)
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#define FLAGS_GIV BIT(2)
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-#define FLAGS_NEW_KEY BIT(4)
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-#define FLAGS_NEW_IV BIT(5)
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-#define FLAGS_INIT BIT(6)
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-#define FLAGS_FAST BIT(7)
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-#define FLAGS_BUSY BIT(8)
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+#define FLAGS_INIT BIT(4)
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+#define FLAGS_FAST BIT(5)
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+#define FLAGS_BUSY BIT(6)
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struct omap_aes_ctx {
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struct omap_aes_dev *dd;
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@@ -105,9 +103,6 @@ struct omap_aes_dev {
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unsigned long flags;
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int err;
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- u32 *iv;
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- u32 ctrl;
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-
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spinlock_t lock;
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struct crypto_queue queue;
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@@ -209,28 +204,13 @@ static int omap_aes_hw_init(struct omap_aes_dev *dd)
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static int omap_aes_write_ctrl(struct omap_aes_dev *dd)
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{
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unsigned int key32;
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- int i, err, init = dd->flags & FLAGS_INIT;
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+ int i, err;
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u32 val, mask;
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err = omap_aes_hw_init(dd);
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if (err)
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return err;
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- val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
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- if (dd->flags & FLAGS_CBC)
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- val |= AES_REG_CTRL_CBC;
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- if (dd->flags & FLAGS_ENCRYPT)
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- val |= AES_REG_CTRL_DIRECTION;
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-
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- /* check if hw state & mode have not changed */
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- if (init && dd->ctrl == val && !(dd->flags & FLAGS_NEW_IV) &&
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- !(dd->ctx->flags & FLAGS_NEW_KEY))
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- goto out;
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-
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- /* only need to write control registers for new settings */
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-
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- dd->ctrl = val;
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-
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val = 0;
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if (dd->dma_lch_out >= 0)
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val |= AES_REG_MASK_DMA_OUT_EN;
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@@ -241,27 +221,28 @@ static int omap_aes_write_ctrl(struct omap_aes_dev *dd)
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omap_aes_write_mask(dd, AES_REG_MASK, val, mask);
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- pr_debug("Set key\n");
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key32 = dd->ctx->keylen / sizeof(u32);
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- /* set a key */
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+
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+ /* it seems a key should always be set even if it has not changed */
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for (i = 0; i < key32; i++) {
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omap_aes_write(dd, AES_REG_KEY(i),
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__le32_to_cpu(dd->ctx->key[i]));
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}
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- dd->ctx->flags &= ~FLAGS_NEW_KEY;
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- if (dd->flags & FLAGS_NEW_IV) {
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- pr_debug("Set IV\n");
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- omap_aes_write_n(dd, AES_REG_IV(0), dd->iv, 4);
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- dd->flags &= ~FLAGS_NEW_IV;
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- }
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+ if ((dd->flags & FLAGS_CBC) && dd->req->info)
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+ omap_aes_write_n(dd, AES_REG_IV(0), dd->req->info, 4);
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+
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+ val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
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+ if (dd->flags & FLAGS_CBC)
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+ val |= AES_REG_CTRL_CBC;
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+ if (dd->flags & FLAGS_ENCRYPT)
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+ val |= AES_REG_CTRL_DIRECTION;
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mask = AES_REG_CTRL_CBC | AES_REG_CTRL_DIRECTION |
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AES_REG_CTRL_KEY_SIZE;
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- omap_aes_write_mask(dd, AES_REG_CTRL, dd->ctrl, mask);
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+ omap_aes_write_mask(dd, AES_REG_CTRL, val, mask);
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-out:
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/* start DMA or disable idle mode */
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omap_aes_write_mask(dd, AES_REG_MASK, AES_REG_MASK_START,
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AES_REG_MASK_START);
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@@ -561,16 +542,12 @@ static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
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static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
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{
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struct ablkcipher_request *req = dd->req;
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- struct omap_aes_ctx *ctx;
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pr_debug("err: %d\n", err);
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dd->flags &= ~FLAGS_BUSY;
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- ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
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-
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- if (req->base.complete)
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- req->base.complete(&req->base, err);
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+ req->base.complete(&req->base, err);
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}
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static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
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@@ -636,8 +613,6 @@ static int omap_aes_handle_queue(struct omap_aes_dev *dd,
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req = ablkcipher_request_cast(async_req);
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- pr_debug("get new req\n");
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-
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/* assign new request to device */
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dd->req = req;
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dd->total = req->nbytes;
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@@ -651,18 +626,8 @@ static int omap_aes_handle_queue(struct omap_aes_dev *dd,
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rctx->mode &= FLAGS_MODE_MASK;
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dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
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- dd->iv = req->info;
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- if ((dd->flags & FLAGS_CBC) && dd->iv)
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- dd->flags |= FLAGS_NEW_IV;
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- else
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- dd->flags &= ~FLAGS_NEW_IV;
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-
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+ dd->ctx = ctx;
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ctx->dd = dd;
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- if (dd->ctx != ctx) {
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- /* assign new context to device */
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- dd->ctx = ctx;
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- ctx->flags |= FLAGS_NEW_KEY;
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- }
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err = omap_aes_crypt_dma_start(dd);
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if (err) {
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@@ -744,7 +709,6 @@ static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
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memcpy(ctx->key, key, keylen);
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ctx->keylen = keylen;
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- ctx->flags |= FLAGS_NEW_KEY;
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return 0;
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}
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