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@@ -38,11 +38,11 @@
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#include <mach/pxa-regs.h>
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#endif
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-#define TIMER_FREQ CLOCK_TICK_RATE
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#define RTC_DEF_DIVIDER 32768 - 1
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#define RTC_DEF_TRIM 0
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static unsigned long rtc_freq = 1024;
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+static unsigned long timer_freq;
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static struct rtc_time rtc_alarm;
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static DEFINE_SPINLOCK(sa1100_rtc_lock);
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@@ -157,7 +157,7 @@ static irqreturn_t timer1_interrupt(int irq, void *dev_id)
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rtc_update_irq(rtc, rtc_timer1_count, RTC_PF | RTC_IRQF);
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if (rtc_timer1_count == 1)
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- rtc_timer1_count = (rtc_freq * ((1<<30)/(TIMER_FREQ>>2)));
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+ rtc_timer1_count = (rtc_freq * ((1 << 30) / (timer_freq >> 2)));
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return IRQ_HANDLED;
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}
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@@ -166,7 +166,7 @@ static int sa1100_rtc_read_callback(struct device *dev, int data)
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{
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if (data & RTC_PF) {
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/* interpolate missed periods and set match for the next */
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- unsigned long period = TIMER_FREQ/rtc_freq;
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+ unsigned long period = timer_freq / rtc_freq;
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unsigned long oscr = OSCR;
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unsigned long osmr1 = OSMR1;
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unsigned long missed = (oscr - osmr1)/period;
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@@ -263,7 +263,7 @@ static int sa1100_rtc_ioctl(struct device *dev, unsigned int cmd,
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return 0;
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case RTC_PIE_ON:
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spin_lock_irq(&sa1100_rtc_lock);
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- OSMR1 = TIMER_FREQ/rtc_freq + OSCR;
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+ OSMR1 = timer_freq / rtc_freq + OSCR;
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OIER |= OIER_E1;
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rtc_timer1_count = 1;
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spin_unlock_irq(&sa1100_rtc_lock);
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@@ -271,7 +271,7 @@ static int sa1100_rtc_ioctl(struct device *dev, unsigned int cmd,
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case RTC_IRQP_READ:
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return put_user(rtc_freq, (unsigned long *)arg);
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case RTC_IRQP_SET:
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- if (arg < 1 || arg > TIMER_FREQ)
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+ if (arg < 1 || arg > timer_freq)
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return -EINVAL;
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rtc_freq = arg;
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return 0;
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@@ -352,6 +352,8 @@ static int sa1100_rtc_probe(struct platform_device *pdev)
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{
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struct rtc_device *rtc;
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+ timer_freq = get_clock_tick_rate();
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+
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/*
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* According to the manual we should be able to let RTTR be zero
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* and then a default diviser for a 32.768KHz clock is used.
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