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@@ -2469,10 +2469,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
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u32 reg, temp;
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/* For PCH output, training FDI link */
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- if (IS_GEN6(dev))
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- gen6_fdi_link_train(crtc);
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- else
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- ironlake_fdi_link_train(crtc);
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+ dev_priv->display.fdi_link_train(crtc);
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intel_enable_pch_pll(dev_priv, pipe);
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@@ -7431,6 +7428,7 @@ static void intel_init_display(struct drm_device *dev)
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"Disable CxSR\n");
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dev_priv->display.update_wm = NULL;
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}
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+ dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
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} else if (IS_GEN6(dev)) {
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if (SNB_READ_WM0_LATENCY()) {
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dev_priv->display.update_wm = sandybridge_update_wm;
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@@ -7439,6 +7437,7 @@ static void intel_init_display(struct drm_device *dev)
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"Disable CxSR\n");
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dev_priv->display.update_wm = NULL;
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}
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+ dev_priv->display.fdi_link_train = gen6_fdi_link_train;
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} else
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dev_priv->display.update_wm = NULL;
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} else if (IS_PINEVIEW(dev)) {
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