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+/******************************************************************************
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+ * Intel Management Engine Interface (Intel MEI) Linux driver
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+ * Intel MEI Interface Header
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+ *
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+ * This file is provided under a dual BSD/GPLv2 license. When using or
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+ * redistributing this file, you may do so under either license.
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+ *
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+ * GPL LICENSE SUMMARY
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+ *
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+ * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of version 2 of the GNU General Public License as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful, but
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+ * WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ * General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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+ * USA
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+ *
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+ * The full GNU General Public License is included in this distribution
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+ * in the file called LICENSE.GPL.
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+ *
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+ * Contact Information:
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+ * Intel Corporation.
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+ * linux-mei@linux.intel.com
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+ * http://www.intel.com
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+ *
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+ * BSD LICENSE
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+ *
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+ * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
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+ * All rights reserved.
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+ *
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+ * Redistribution and use in source and binary forms, with or without
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+ * modification, are permitted provided that the following conditions
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+ * are met:
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+ *
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+ * * Redistributions of source code must retain the above copyright
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+ * notice, this list of conditions and the following disclaimer.
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+ * * Redistributions in binary form must reproduce the above copyright
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+ * notice, this list of conditions and the following disclaimer in
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+ * the documentation and/or other materials provided with the
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+ * distribution.
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+ * * Neither the name Intel Corporation nor the names of its
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+ * contributors may be used to endorse or promote products derived
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+ * from this software without specific prior written permission.
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+ *
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+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+ *
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+ *****************************************************************************/
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+#ifndef _MEI_HW_MEI_H_
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+#define _MEI_HW_MEI_H_
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+
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+/*
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+ * MEI device IDs
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+ */
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+#define MEI_DEV_ID_82946GZ 0x2974 /* 82946GZ/GL */
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+#define MEI_DEV_ID_82G35 0x2984 /* 82G35 Express */
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+#define MEI_DEV_ID_82Q965 0x2994 /* 82Q963/Q965 */
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+#define MEI_DEV_ID_82G965 0x29A4 /* 82P965/G965 */
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+
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+#define MEI_DEV_ID_82GM965 0x2A04 /* Mobile PM965/GM965 */
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+#define MEI_DEV_ID_82GME965 0x2A14 /* Mobile GME965/GLE960 */
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+
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+#define MEI_DEV_ID_ICH9_82Q35 0x29B4 /* 82Q35 Express */
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+#define MEI_DEV_ID_ICH9_82G33 0x29C4 /* 82G33/G31/P35/P31 Express */
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+#define MEI_DEV_ID_ICH9_82Q33 0x29D4 /* 82Q33 Express */
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+#define MEI_DEV_ID_ICH9_82X38 0x29E4 /* 82X38/X48 Express */
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+#define MEI_DEV_ID_ICH9_3200 0x29F4 /* 3200/3210 Server */
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+
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+#define MEI_DEV_ID_ICH9_6 0x28B4 /* Bearlake */
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+#define MEI_DEV_ID_ICH9_7 0x28C4 /* Bearlake */
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+#define MEI_DEV_ID_ICH9_8 0x28D4 /* Bearlake */
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+#define MEI_DEV_ID_ICH9_9 0x28E4 /* Bearlake */
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+#define MEI_DEV_ID_ICH9_10 0x28F4 /* Bearlake */
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+
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+#define MEI_DEV_ID_ICH9M_1 0x2A44 /* Cantiga */
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+#define MEI_DEV_ID_ICH9M_2 0x2A54 /* Cantiga */
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+#define MEI_DEV_ID_ICH9M_3 0x2A64 /* Cantiga */
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+#define MEI_DEV_ID_ICH9M_4 0x2A74 /* Cantiga */
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+
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+#define MEI_DEV_ID_ICH10_1 0x2E04 /* Eaglelake */
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+#define MEI_DEV_ID_ICH10_2 0x2E14 /* Eaglelake */
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+#define MEI_DEV_ID_ICH10_3 0x2E24 /* Eaglelake */
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+#define MEI_DEV_ID_ICH10_4 0x2E34 /* Eaglelake */
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+
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+#define MEI_DEV_ID_IBXPK_1 0x3B64 /* Calpella */
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+#define MEI_DEV_ID_IBXPK_2 0x3B65 /* Calpella */
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+
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+#define MEI_DEV_ID_CPT_1 0x1C3A /* Couger Point */
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+#define MEI_DEV_ID_PBG_1 0x1D3A /* C600/X79 Patsburg */
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+
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+#define MEI_DEV_ID_PPT_1 0x1E3A /* Panther Point */
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+#define MEI_DEV_ID_PPT_2 0x1CBA /* Panther Point */
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+#define MEI_DEV_ID_PPT_3 0x1DBA /* Panther Point */
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+
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+#define MEI_DEV_ID_LPT 0x8C3A /* Lynx Point */
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+#define MEI_DEV_ID_LPT_LP 0x9C3A /* Lynx Point LP */
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+/*
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+ * MEI HW Section
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+ */
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+
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+/* MEI registers */
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+/* H_CB_WW - Host Circular Buffer (CB) Write Window register */
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+#define H_CB_WW 0
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+/* H_CSR - Host Control Status register */
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+#define H_CSR 4
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+/* ME_CB_RW - ME Circular Buffer Read Window register (read only) */
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+#define ME_CB_RW 8
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+/* ME_CSR_HA - ME Control Status Host Access register (read only) */
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+#define ME_CSR_HA 0xC
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+
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+
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+/* register bits of H_CSR (Host Control Status register) */
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+/* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
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+#define H_CBD 0xFF000000
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+/* Host Circular Buffer Write Pointer */
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+#define H_CBWP 0x00FF0000
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+/* Host Circular Buffer Read Pointer */
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+#define H_CBRP 0x0000FF00
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+/* Host Reset */
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+#define H_RST 0x00000010
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+/* Host Ready */
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+#define H_RDY 0x00000008
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+/* Host Interrupt Generate */
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+#define H_IG 0x00000004
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+/* Host Interrupt Status */
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+#define H_IS 0x00000002
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+/* Host Interrupt Enable */
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+#define H_IE 0x00000001
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+
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+
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+/* register bits of ME_CSR_HA (ME Control Status Host Access register) */
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+/* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only
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+access to ME_CBD */
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+#define ME_CBD_HRA 0xFF000000
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+/* ME CB Write Pointer HRA - host read only access to ME_CBWP */
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+#define ME_CBWP_HRA 0x00FF0000
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+/* ME CB Read Pointer HRA - host read only access to ME_CBRP */
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+#define ME_CBRP_HRA 0x0000FF00
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+/* ME Reset HRA - host read only access to ME_RST */
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+#define ME_RST_HRA 0x00000010
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+/* ME Ready HRA - host read only access to ME_RDY */
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+#define ME_RDY_HRA 0x00000008
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+/* ME Interrupt Generate HRA - host read only access to ME_IG */
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+#define ME_IG_HRA 0x00000004
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+/* ME Interrupt Status HRA - host read only access to ME_IS */
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+#define ME_IS_HRA 0x00000002
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+/* ME Interrupt Enable HRA - host read only access to ME_IE */
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+#define ME_IE_HRA 0x00000001
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+
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+#endif /* _MEI_HW_MEI_H_ */
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Tomas Winkler