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@@ -65,6 +65,7 @@ struct mxs_gpio_port {
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struct irq_domain *domain;
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struct bgpio_chip bgc;
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enum mxs_gpio_id devid;
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+ u32 both_edges;
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};
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static inline int is_imx23_gpio(struct mxs_gpio_port *port)
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@@ -81,13 +82,23 @@ static inline int is_imx28_gpio(struct mxs_gpio_port *port)
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static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
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{
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+ u32 val;
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u32 pin_mask = 1 << d->hwirq;
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct mxs_gpio_port *port = gc->private;
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void __iomem *pin_addr;
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int edge;
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+ port->both_edges &= ~pin_mask;
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switch (type) {
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+ case IRQ_TYPE_EDGE_BOTH:
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+ val = gpio_get_value(port->bgc.gc.base + d->hwirq);
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+ if (val)
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+ edge = GPIO_INT_FALL_EDGE;
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+ else
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+ edge = GPIO_INT_RISE_EDGE;
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+ port->both_edges |= pin_mask;
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+ break;
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case IRQ_TYPE_EDGE_RISING:
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edge = GPIO_INT_RISE_EDGE;
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break;
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@@ -124,6 +135,23 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
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return 0;
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}
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+static void mxs_flip_edge(struct mxs_gpio_port *port, u32 gpio)
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+{
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+ u32 bit, val, edge;
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+ void __iomem *pin_addr;
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+
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+ bit = 1 << gpio;
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+
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+ pin_addr = port->base + PINCTRL_IRQPOL(port);
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+ val = readl(pin_addr);
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+ edge = val & bit;
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+
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+ if (edge)
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+ writel(bit, pin_addr + MXS_CLR);
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+ else
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+ writel(bit, pin_addr + MXS_SET);
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+}
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+
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/* MXS has one interrupt *per* gpio port */
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static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
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{
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@@ -137,6 +165,9 @@ static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
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while (irq_stat != 0) {
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int irqoffset = fls(irq_stat) - 1;
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+ if (port->both_edges & (1 << irqoffset))
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+ mxs_flip_edge(port, irqoffset);
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+
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generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
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irq_stat &= ~(1 << irqoffset);
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}
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