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@@ -752,42 +752,6 @@ static void tg3_int_reenable(struct tg3_napi *tnapi)
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HOSTCC_MODE_ENABLE | tnapi->coal_now);
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}
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-static void tg3_napi_disable(struct tg3 *tp)
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-{
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- int i;
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-
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- for (i = tp->irq_cnt - 1; i >= 0; i--)
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- napi_disable(&tp->napi[i].napi);
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-}
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-
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-static void tg3_napi_enable(struct tg3 *tp)
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-{
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- int i;
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-
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- for (i = 0; i < tp->irq_cnt; i++)
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- napi_enable(&tp->napi[i].napi);
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-}
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-
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-static inline void tg3_netif_stop(struct tg3 *tp)
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-{
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- tp->dev->trans_start = jiffies; /* prevent tx timeout */
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- tg3_napi_disable(tp);
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- netif_tx_disable(tp->dev);
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-}
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-
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-static inline void tg3_netif_start(struct tg3 *tp)
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-{
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- /* NOTE: unconditional netif_tx_wake_all_queues is only
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- * appropriate so long as all callers are assured to
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- * have free tx slots (such as after tg3_init_hw)
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- */
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- netif_tx_wake_all_queues(tp->dev);
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-
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- tg3_napi_enable(tp);
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- tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
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- tg3_enable_ints(tp);
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-}
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-
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static void tg3_switch_clocks(struct tg3 *tp)
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{
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u32 clock_ctrl;
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@@ -4338,6 +4302,11 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
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return err;
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}
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+static inline int tg3_irq_sync(struct tg3 *tp)
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+{
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+ return tp->irq_sync;
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+}
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+
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/* This is called whenever we suspect that the system chipset is re-
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* ordering the sequence of MMIO to the tx send mailbox. The symptom
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* is bogus tx completions. We try to recover by setting the
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@@ -5083,6 +5052,59 @@ tx_recovery:
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return work_done;
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}
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+static void tg3_napi_disable(struct tg3 *tp)
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+{
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+ int i;
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+
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+ for (i = tp->irq_cnt - 1; i >= 0; i--)
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+ napi_disable(&tp->napi[i].napi);
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+}
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+
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+static void tg3_napi_enable(struct tg3 *tp)
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+{
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+ int i;
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+
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+ for (i = 0; i < tp->irq_cnt; i++)
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+ napi_enable(&tp->napi[i].napi);
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+}
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+
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+static void tg3_napi_init(struct tg3 *tp)
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+{
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+ int i;
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+
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+ netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
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+ for (i = 1; i < tp->irq_cnt; i++)
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+ netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
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+}
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+
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+static void tg3_napi_fini(struct tg3 *tp)
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+{
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+ int i;
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+
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+ for (i = 0; i < tp->irq_cnt; i++)
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+ netif_napi_del(&tp->napi[i].napi);
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+}
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+
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+static inline void tg3_netif_stop(struct tg3 *tp)
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+{
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+ tp->dev->trans_start = jiffies; /* prevent tx timeout */
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+ tg3_napi_disable(tp);
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+ netif_tx_disable(tp->dev);
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+}
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+
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+static inline void tg3_netif_start(struct tg3 *tp)
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+{
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+ /* NOTE: unconditional netif_tx_wake_all_queues is only
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+ * appropriate so long as all callers are assured to
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+ * have free tx slots (such as after tg3_init_hw)
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+ */
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+ netif_tx_wake_all_queues(tp->dev);
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+
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+ tg3_napi_enable(tp);
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+ tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
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+ tg3_enable_ints(tp);
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+}
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+
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static void tg3_irq_quiesce(struct tg3 *tp)
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{
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int i;
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@@ -5096,11 +5118,6 @@ static void tg3_irq_quiesce(struct tg3 *tp)
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synchronize_irq(tp->napi[i].irq_vec);
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}
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-static inline int tg3_irq_sync(struct tg3 *tp)
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-{
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- return tp->irq_sync;
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-}
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-
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/* Fully shutdown all tg3 driver activity elsewhere in the system.
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* If irq_sync is non-zero, then the IRQ handler must be synchronized
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* with as well. Most of the time, this is not necessary except when
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@@ -8920,6 +8937,8 @@ static int tg3_open(struct net_device *dev)
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if (err)
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goto err_out1;
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+ tg3_napi_init(tp);
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+
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tg3_napi_enable(tp);
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for (i = 0; i < tp->irq_cnt; i++) {
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@@ -9007,6 +9026,7 @@ err_out3:
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err_out2:
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tg3_napi_disable(tp);
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+ tg3_napi_fini(tp);
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tg3_free_consistent(tp);
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err_out1:
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@@ -9054,6 +9074,8 @@ static int tg3_close(struct net_device *dev)
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memcpy(&tp->estats_prev, tg3_get_estats(tp),
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sizeof(tp->estats_prev));
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+ tg3_napi_fini(tp);
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+
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tg3_free_consistent(tp);
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tg3_set_power_state(tp, PCI_D3hot);
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@@ -14604,13 +14626,10 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
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tnapi->consmbox = rcvmbx;
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tnapi->prodmbox = sndmbx;
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- if (i) {
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+ if (i)
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tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
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- netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
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- } else {
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+ else
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tnapi->coal_now = HOSTCC_MODE_NOW;
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- netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
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- }
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if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
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break;
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