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@@ -258,7 +258,7 @@ static int pcie_write_cmd(struct slot *slot, u16 cmd, u16 mask)
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retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
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if (retval) {
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- err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
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+ err("%s: Cannot read SLOTSTATUS register\n", __func__);
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goto out;
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}
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@@ -267,13 +267,13 @@ static int pcie_write_cmd(struct slot *slot, u16 cmd, u16 mask)
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proceed forward to issue the next command according
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to spec. Just print out the error message */
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dbg("%s: CMD_COMPLETED not clear after 1 sec.\n",
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- __FUNCTION__);
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+ __func__);
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}
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spin_lock_irqsave(&ctrl->lock, flags);
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retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
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if (retval) {
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- err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
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+ err("%s: Cannot read SLOTCTRL register\n", __func__);
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goto out_spin_unlock;
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}
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@@ -283,7 +283,7 @@ static int pcie_write_cmd(struct slot *slot, u16 cmd, u16 mask)
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ctrl->cmd_busy = 1;
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retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
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if (retval)
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- err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
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+ err("%s: Cannot write to SLOTCTRL register\n", __func__);
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out_spin_unlock:
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spin_unlock_irqrestore(&ctrl->lock, flags);
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@@ -305,14 +305,14 @@ static int hpc_check_lnk_status(struct controller *ctrl)
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retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
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if (retval) {
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- err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
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+ err("%s: Cannot read LNKSTATUS register\n", __func__);
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return retval;
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}
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- dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status);
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+ dbg("%s: lnk_status = %x\n", __func__, lnk_status);
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if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
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!(lnk_status & NEG_LINK_WD)) {
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- err("%s : Link Training Error occurs \n", __FUNCTION__);
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+ err("%s : Link Training Error occurs \n", __func__);
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retval = -1;
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return retval;
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}
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@@ -329,12 +329,12 @@ static int hpc_get_attention_status(struct slot *slot, u8 *status)
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retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
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if (retval) {
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- err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
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+ err("%s: Cannot read SLOTCTRL register\n", __func__);
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return retval;
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}
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dbg("%s: SLOTCTRL %x, value read %x\n",
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- __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
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+ __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
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atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
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@@ -368,11 +368,11 @@ static int hpc_get_power_status(struct slot *slot, u8 *status)
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retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
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if (retval) {
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- err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
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+ err("%s: Cannot read SLOTCTRL register\n", __func__);
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return retval;
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}
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dbg("%s: SLOTCTRL %x value read %x\n",
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- __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
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+ __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
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pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
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@@ -399,7 +399,7 @@ static int hpc_get_latch_status(struct slot *slot, u8 *status)
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retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
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if (retval) {
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- err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
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+ err("%s: Cannot read SLOTSTATUS register\n", __func__);
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return retval;
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}
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@@ -417,7 +417,7 @@ static int hpc_get_adapter_status(struct slot *slot, u8 *status)
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retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
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if (retval) {
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- err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
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+ err("%s: Cannot read SLOTSTATUS register\n", __func__);
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return retval;
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}
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card_state = (u8)((slot_status & PRSN_STATE) >> 6);
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@@ -435,7 +435,7 @@ static int hpc_query_power_fault(struct slot *slot)
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retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
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if (retval) {
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- err("%s: Cannot check for power fault\n", __FUNCTION__);
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+ err("%s: Cannot check for power fault\n", __func__);
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return retval;
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}
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pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
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@@ -451,7 +451,7 @@ static int hpc_get_emi_status(struct slot *slot, u8 *status)
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retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
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if (retval) {
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- err("%s : Cannot check EMI status\n", __FUNCTION__);
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+ err("%s : Cannot check EMI status\n", __func__);
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return retval;
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}
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*status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT;
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@@ -506,7 +506,7 @@ static int hpc_set_attention_status(struct slot *slot, u8 value)
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rc = pcie_write_cmd(slot, slot_cmd, cmd_mask);
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dbg("%s: SLOTCTRL %x write cmd %x\n",
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- __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
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+ __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
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return rc;
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}
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@@ -527,7 +527,7 @@ static void hpc_set_green_led_on(struct slot *slot)
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pcie_write_cmd(slot, slot_cmd, cmd_mask);
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dbg("%s: SLOTCTRL %x write cmd %x\n",
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- __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
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+ __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
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}
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static void hpc_set_green_led_off(struct slot *slot)
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@@ -545,7 +545,7 @@ static void hpc_set_green_led_off(struct slot *slot)
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pcie_write_cmd(slot, slot_cmd, cmd_mask);
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dbg("%s: SLOTCTRL %x write cmd %x\n",
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- __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
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+ __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
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}
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static void hpc_set_green_led_blink(struct slot *slot)
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@@ -564,7 +564,7 @@ static void hpc_set_green_led_blink(struct slot *slot)
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pcie_write_cmd(slot, slot_cmd, cmd_mask);
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dbg("%s: SLOTCTRL %x write cmd %x\n",
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- __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
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+ __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
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}
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static void hpc_release_ctlr(struct controller *ctrl)
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@@ -590,12 +590,12 @@ static int hpc_power_on_slot(struct slot * slot)
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u16 slot_status;
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int retval = 0;
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- dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
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+ dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
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/* Clear sticky power-fault bit from previous power failures */
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retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
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if (retval) {
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- err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
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+ err("%s: Cannot read SLOTSTATUS register\n", __func__);
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return retval;
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}
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slot_status &= PWR_FAULT_DETECTED;
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@@ -603,7 +603,7 @@ static int hpc_power_on_slot(struct slot * slot)
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retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status);
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if (retval) {
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err("%s: Cannot write to SLOTSTATUS register\n",
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- __FUNCTION__);
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+ __func__);
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return retval;
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}
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}
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@@ -627,11 +627,11 @@ static int hpc_power_on_slot(struct slot * slot)
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retval = pcie_write_cmd(slot, slot_cmd, cmd_mask);
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if (retval) {
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- err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
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+ err("%s: Write %x command failed!\n", __func__, slot_cmd);
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return -1;
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}
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dbg("%s: SLOTCTRL %x write cmd %x\n",
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- __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
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+ __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
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return retval;
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}
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@@ -677,7 +677,7 @@ static int hpc_power_off_slot(struct slot * slot)
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int retval = 0;
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int changed;
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- dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
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+ dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
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/*
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* Set Bad DLLP Mask bit in Correctable Error Mask
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@@ -710,12 +710,12 @@ static int hpc_power_off_slot(struct slot * slot)
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retval = pcie_write_cmd(slot, slot_cmd, cmd_mask);
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if (retval) {
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- err("%s: Write command failed!\n", __FUNCTION__);
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+ err("%s: Write command failed!\n", __func__);
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retval = -1;
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goto out;
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}
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dbg("%s: SLOTCTRL %x write cmd %x\n",
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- __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
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+ __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
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/*
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* After turning power off, we must wait for at least 1 second
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@@ -741,7 +741,7 @@ static irqreturn_t pcie_isr(int irq, void *dev_id)
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rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
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if (rc) {
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- err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
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+ err("%s: Cannot read SLOTSTATUS register\n", __func__);
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return IRQ_NONE;
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}
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@@ -754,26 +754,26 @@ static irqreturn_t pcie_isr(int irq, void *dev_id)
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if ( !intr_loc )
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return IRQ_NONE;
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- dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
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+ dbg("%s: intr_loc %x\n", __func__, intr_loc);
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/* Mask Hot-plug Interrupt Enable */
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if (!pciehp_poll_mode) {
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spin_lock_irqsave(&ctrl->lock, flags);
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rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
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if (rc) {
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err("%s: Cannot read SLOT_CTRL register\n",
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- __FUNCTION__);
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+ __func__);
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spin_unlock_irqrestore(&ctrl->lock, flags);
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return IRQ_NONE;
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}
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dbg("%s: pciehp_readw(SLOTCTRL) with value %x\n",
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- __FUNCTION__, temp_word);
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+ __func__, temp_word);
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temp_word = (temp_word & ~HP_INTR_ENABLE &
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~CMD_CMPL_INTR_ENABLE) | 0x00;
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rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
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if (rc) {
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err("%s: Cannot write to SLOTCTRL register\n",
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- __FUNCTION__);
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+ __func__);
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spin_unlock_irqrestore(&ctrl->lock, flags);
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return IRQ_NONE;
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}
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@@ -782,18 +782,18 @@ static irqreturn_t pcie_isr(int irq, void *dev_id)
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rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
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if (rc) {
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err("%s: Cannot read SLOT_STATUS register\n",
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- __FUNCTION__);
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+ __func__);
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return IRQ_NONE;
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}
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dbg("%s: pciehp_readw(SLOTSTATUS) with value %x\n",
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- __FUNCTION__, slot_status);
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+ __func__, slot_status);
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/* Clear command complete interrupt caused by this write */
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temp_word = 0x1f;
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rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
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if (rc) {
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err("%s: Cannot write to SLOTSTATUS register\n",
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- __FUNCTION__);
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+ __func__);
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return IRQ_NONE;
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}
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}
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@@ -822,7 +822,7 @@ static irqreturn_t pcie_isr(int irq, void *dev_id)
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temp_word = 0x1F;
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rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
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if (rc) {
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- err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
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+ err("%s: Cannot write to SLOTSTATUS register\n", __func__);
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return IRQ_NONE;
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}
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/* Unmask Hot-plug Interrupt Enable */
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@@ -831,18 +831,18 @@ static irqreturn_t pcie_isr(int irq, void *dev_id)
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rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
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if (rc) {
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err("%s: Cannot read SLOTCTRL register\n",
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- __FUNCTION__);
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+ __func__);
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spin_unlock_irqrestore(&ctrl->lock, flags);
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return IRQ_NONE;
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}
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- dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
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+ dbg("%s: Unmask Hot-plug Interrupt Enable\n", __func__);
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temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
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rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
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if (rc) {
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err("%s: Cannot write to SLOTCTRL register\n",
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- __FUNCTION__);
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+ __func__);
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spin_unlock_irqrestore(&ctrl->lock, flags);
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return IRQ_NONE;
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}
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@@ -851,7 +851,7 @@ static irqreturn_t pcie_isr(int irq, void *dev_id)
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rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
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if (rc) {
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err("%s: Cannot read SLOT_STATUS register\n",
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- __FUNCTION__);
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+ __func__);
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return IRQ_NONE;
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}
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@@ -860,11 +860,11 @@ static irqreturn_t pcie_isr(int irq, void *dev_id)
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rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
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if (rc) {
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err("%s: Cannot write to SLOTSTATUS failed\n",
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- __FUNCTION__);
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+ __func__);
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return IRQ_NONE;
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}
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dbg("%s: pciehp_writew(SLOTSTATUS) with value %x\n",
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- __FUNCTION__, temp_word);
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+ __func__, temp_word);
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}
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return IRQ_HANDLED;
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@@ -879,7 +879,7 @@ static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
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retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
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if (retval) {
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- err("%s: Cannot read LNKCAP register\n", __FUNCTION__);
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+ err("%s: Cannot read LNKCAP register\n", __func__);
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return retval;
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}
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@@ -908,7 +908,7 @@ static int hpc_get_max_lnk_width(struct slot *slot,
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retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
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if (retval) {
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- err("%s: Cannot read LNKCAP register\n", __FUNCTION__);
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+ err("%s: Cannot read LNKCAP register\n", __func__);
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return retval;
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}
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@@ -957,7 +957,7 @@ static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
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retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
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if (retval) {
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- err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
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+ err("%s: Cannot read LNKSTATUS register\n", __func__);
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return retval;
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}
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@@ -986,7 +986,7 @@ static int hpc_get_cur_lnk_width(struct slot *slot,
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retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
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if (retval) {
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- err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
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+ err("%s: Cannot read LNKSTATUS register\n", __func__);
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return retval;
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}
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@@ -1130,38 +1130,38 @@ static int pcie_init_hardware_part1(struct controller *ctrl,
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rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
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if (rc) {
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- err("%s: Cannot read SLOTCAP register\n", __FUNCTION__);
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+ err("%s: Cannot read SLOTCAP register\n", __func__);
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return -1;
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}
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|
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/* Mask Hot-plug Interrupt Enable */
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|
|
rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
|
|
|
if (rc) {
|
|
|
- err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
|
|
|
+ err("%s: Cannot read SLOTCTRL register\n", __func__);
|
|
|
return -1;
|
|
|
}
|
|
|
|
|
|
dbg("%s: SLOTCTRL %x value read %x\n",
|
|
|
- __FUNCTION__, ctrl->cap_base + SLOTCTRL, temp_word);
|
|
|
+ __func__, ctrl->cap_base + SLOTCTRL, temp_word);
|
|
|
temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) |
|
|
|
0x00;
|
|
|
|
|
|
rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
|
|
|
if (rc) {
|
|
|
- err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
|
|
|
+ err("%s: Cannot write to SLOTCTRL register\n", __func__);
|
|
|
return -1;
|
|
|
}
|
|
|
|
|
|
rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
|
|
|
if (rc) {
|
|
|
- err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
|
|
|
+ err("%s: Cannot read SLOTSTATUS register\n", __func__);
|
|
|
return -1;
|
|
|
}
|
|
|
|
|
|
temp_word = 0x1F; /* Clear all events */
|
|
|
rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
|
|
|
if (rc) {
|
|
|
- err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
|
|
|
+ err("%s: Cannot write to SLOTSTATUS register\n", __func__);
|
|
|
return -1;
|
|
|
}
|
|
|
return 0;
|
|
@@ -1177,7 +1177,7 @@ int pcie_init_hardware_part2(struct controller *ctrl, struct pcie_device *dev)
|
|
|
|
|
|
rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
|
|
|
if (rc) {
|
|
|
- err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
|
|
|
+ err("%s: Cannot read SLOTCTRL register\n", __func__);
|
|
|
goto abort;
|
|
|
}
|
|
|
|
|
@@ -1185,7 +1185,7 @@ int pcie_init_hardware_part2(struct controller *ctrl, struct pcie_device *dev)
|
|
|
|
|
|
rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
|
|
|
if (rc) {
|
|
|
- err("%s: Cannot read SLOTCAP register\n", __FUNCTION__);
|
|
|
+ err("%s: Cannot read SLOTCAP register\n", __func__);
|
|
|
goto abort;
|
|
|
}
|
|
|
|
|
@@ -1212,19 +1212,19 @@ int pcie_init_hardware_part2(struct controller *ctrl, struct pcie_device *dev)
|
|
|
*/
|
|
|
rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
|
|
|
if (rc) {
|
|
|
- err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
|
|
|
+ err("%s: Cannot write to SLOTCTRL register\n", __func__);
|
|
|
goto abort;
|
|
|
}
|
|
|
rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
|
|
|
if (rc) {
|
|
|
- err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
|
|
|
+ err("%s: Cannot read SLOTSTATUS register\n", __func__);
|
|
|
goto abort_disable_intr;
|
|
|
}
|
|
|
|
|
|
temp_word = 0x1F; /* Clear all events */
|
|
|
rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
|
|
|
if (rc) {
|
|
|
- err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
|
|
|
+ err("%s: Cannot write to SLOTSTATUS register\n", __func__);
|
|
|
goto abort_disable_intr;
|
|
|
}
|
|
|
|
|
@@ -1247,7 +1247,7 @@ abort_disable_intr:
|
|
|
rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
|
|
|
}
|
|
|
if (rc)
|
|
|
- err("%s : disabling interrupts failed\n", __FUNCTION__);
|
|
|
+ err("%s : disabling interrupts failed\n", __func__);
|
|
|
abort:
|
|
|
return -1;
|
|
|
}
|
|
@@ -1265,62 +1265,62 @@ int pcie_init(struct controller *ctrl, struct pcie_device *dev)
|
|
|
ctrl->pci_dev = pdev; /* save pci_dev in context */
|
|
|
|
|
|
dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
|
|
|
- __FUNCTION__, pdev->vendor, pdev->device);
|
|
|
+ __func__, pdev->vendor, pdev->device);
|
|
|
|
|
|
cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
|
|
|
if (cap_base == 0) {
|
|
|
- dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
|
|
|
+ dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __func__);
|
|
|
goto abort;
|
|
|
}
|
|
|
|
|
|
ctrl->cap_base = cap_base;
|
|
|
|
|
|
- dbg("%s: pcie_cap_base %x\n", __FUNCTION__, cap_base);
|
|
|
+ dbg("%s: pcie_cap_base %x\n", __func__, cap_base);
|
|
|
|
|
|
rc = pciehp_readw(ctrl, CAPREG, &cap_reg);
|
|
|
if (rc) {
|
|
|
- err("%s: Cannot read CAPREG register\n", __FUNCTION__);
|
|
|
+ err("%s: Cannot read CAPREG register\n", __func__);
|
|
|
goto abort;
|
|
|
}
|
|
|
dbg("%s: CAPREG offset %x cap_reg %x\n",
|
|
|
- __FUNCTION__, ctrl->cap_base + CAPREG, cap_reg);
|
|
|
+ __func__, ctrl->cap_base + CAPREG, cap_reg);
|
|
|
|
|
|
if (((cap_reg & SLOT_IMPL) == 0) ||
|
|
|
(((cap_reg & DEV_PORT_TYPE) != 0x0040)
|
|
|
&& ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
|
|
|
dbg("%s : This is not a root port or the port is not "
|
|
|
- "connected to a slot\n", __FUNCTION__);
|
|
|
+ "connected to a slot\n", __func__);
|
|
|
goto abort;
|
|
|
}
|
|
|
|
|
|
rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
|
|
|
if (rc) {
|
|
|
- err("%s: Cannot read SLOTCAP register\n", __FUNCTION__);
|
|
|
+ err("%s: Cannot read SLOTCAP register\n", __func__);
|
|
|
goto abort;
|
|
|
}
|
|
|
dbg("%s: SLOTCAP offset %x slot_cap %x\n",
|
|
|
- __FUNCTION__, ctrl->cap_base + SLOTCAP, slot_cap);
|
|
|
+ __func__, ctrl->cap_base + SLOTCAP, slot_cap);
|
|
|
|
|
|
if (!(slot_cap & HP_CAP)) {
|
|
|
- dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
|
|
|
+ dbg("%s : This slot is not hot-plug capable\n", __func__);
|
|
|
goto abort;
|
|
|
}
|
|
|
/* For debugging purpose */
|
|
|
rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
|
|
|
if (rc) {
|
|
|
- err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
|
|
|
+ err("%s: Cannot read SLOTSTATUS register\n", __func__);
|
|
|
goto abort;
|
|
|
}
|
|
|
dbg("%s: SLOTSTATUS offset %x slot_status %x\n",
|
|
|
- __FUNCTION__, ctrl->cap_base + SLOTSTATUS, slot_status);
|
|
|
+ __func__, ctrl->cap_base + SLOTSTATUS, slot_status);
|
|
|
|
|
|
rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
|
|
|
if (rc) {
|
|
|
- err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
|
|
|
+ err("%s: Cannot read SLOTCTRL register\n", __func__);
|
|
|
goto abort;
|
|
|
}
|
|
|
dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n",
|
|
|
- __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
|
|
|
+ __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
|
|
|
|
|
|
for (rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
|
|
|
if (pci_resource_len(pdev, rc) > 0)
|
|
@@ -1358,7 +1358,7 @@ int pcie_init(struct controller *ctrl, struct pcie_device *dev)
|
|
|
rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED,
|
|
|
MY_NAME, (void *)ctrl);
|
|
|
dbg("%s: request_irq %d for hpc%d (returns %d)\n",
|
|
|
- __FUNCTION__, ctrl->pci_dev->irq,
|
|
|
+ __func__, ctrl->pci_dev->irq,
|
|
|
atomic_read(&pciehp_num_controllers), rc);
|
|
|
if (rc) {
|
|
|
err("Can't get irq %d for the hotplug controller\n",
|