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@@ -527,6 +527,7 @@ static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
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*
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* ibm,plb-pciex-440spe
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* ibm,plb-pciex-405ex
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+ * ibm,plb-pciex-460ex
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*
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* Anything else will be rejected for now as they are all subtly
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* different unfortunately.
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@@ -775,6 +776,117 @@ static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
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.setup_utl = ppc440speB_pciex_init_utl,
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};
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+static int __init ppc460ex_pciex_core_init(struct device_node *np)
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+{
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+ /* Nothing to do, return 2 ports */
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+ return 2;
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+}
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+
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+static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
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+{
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+ u32 val;
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+ u32 utlset1;
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+
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+ if (port->endpoint) {
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+ val = PTYPE_LEGACY_ENDPOINT << 20;
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+ utlset1 = 0x20222222;
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+ } else {
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+ val = PTYPE_ROOT_PORT << 20;
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+ utlset1 = 0x21222222;
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+ }
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+
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+ if (port->index == 0) {
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+ val |= LNKW_X1 << 12;
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+ } else {
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+ val |= LNKW_X4 << 12;
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+ utlset1 |= 0x00101101;
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+ }
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+
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+ mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
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+ mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
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+ mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
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+
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+ switch (port->index) {
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+ case 0:
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+ mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
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+ mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000136);
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+ mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
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+
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+ mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
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+ break;
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+
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+ case 1:
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+ mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);
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+ mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
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+ mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
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+ mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
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+ mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000136);
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+ mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000136);
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+ mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000136);
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+ mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000136);
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+ mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
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+ mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
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+ mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);
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+ mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);
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+
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+ mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000);
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+ break;
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+ }
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+
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+ mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
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+ mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
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+ (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
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+
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+ /* Poll for PHY reset */
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+ /* XXX FIXME add timeout */
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+ switch (port->index) {
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+ case 0:
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+ while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1))
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+ udelay(10);
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+ break;
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+ case 1:
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+ while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1))
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+ udelay(10);
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+ break;
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+ }
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+
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+ mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
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+ (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
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+ ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
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+ PESDRx_RCSSET_RSTPYN);
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+
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+ port->has_ibpre = 1;
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+
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+ return 0;
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+}
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+
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+static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
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+{
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+ dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
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+
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+ /*
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+ * Set buffer allocations and then assert VRB and TXE.
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+ */
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+ out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c);
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+ out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
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+ out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
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+ out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
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+ out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000);
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+ out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
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+ out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
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+ out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
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+ out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
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+
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+ return 0;
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+}
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+
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+static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
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+{
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+ .core_init = ppc460ex_pciex_core_init,
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+ .port_init_hw = ppc460ex_pciex_init_port_hw,
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+ .setup_utl = ppc460ex_pciex_init_utl,
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+};
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+
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#endif /* CONFIG_44x */
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#ifdef CONFIG_40x
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@@ -896,6 +1008,8 @@ static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
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else
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ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
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}
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+ if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
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+ ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
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#endif /* CONFIG_44x */
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#ifdef CONFIG_40x
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if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
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