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@@ -3465,23 +3465,23 @@ static void hwi_enable_intr(struct beiscsi_hba *phba)
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addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
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PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
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reg = ioread32(addr);
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- SE_DEBUG(DBG_LVL_8, "reg =x%08x\n", reg);
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enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
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if (!enabled) {
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reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
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SE_DEBUG(DBG_LVL_8, "reg =x%08x addr=%p\n", reg, addr);
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iowrite32(reg, addr);
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- if (!phba->msix_enabled) {
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- eq = &phwi_context->be_eq[0].q;
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+ }
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+
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+ if (!phba->msix_enabled) {
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+ eq = &phwi_context->be_eq[0].q;
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+ SE_DEBUG(DBG_LVL_8, "eq->id=%d\n", eq->id);
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+ hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
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+ } else {
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+ for (i = 0; i <= phba->num_cpus; i++) {
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+ eq = &phwi_context->be_eq[i].q;
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SE_DEBUG(DBG_LVL_8, "eq->id=%d\n", eq->id);
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hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
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- } else {
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- for (i = 0; i <= phba->num_cpus; i++) {
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- eq = &phwi_context->be_eq[i].q;
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- SE_DEBUG(DBG_LVL_8, "eq->id=%d\n", eq->id);
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- hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
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- }
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}
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}
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}
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