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@@ -40,62 +40,6 @@
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#include <linux/mtd/partitions.h>
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#include <linux/delay.h>
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-#if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR)
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-#define CC_GCR 0xB4013818
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-#define CC_GPBCR 0xB401380A
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-#define CC_GPBDR 0xB4013808
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-#define CC_M68K_DEVICE 1
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-#define CC_M68K_FUNCTION 6
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-#define CC_CONFADDR 0xB8004000
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-#define CC_CONFDATA 0xB8004004
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-#define CC_FC_FCR 0xB8002004
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-#define CC_FC_DCR 0xB8002008
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-#define CC_GPACR 0xB4013802
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-#define CC_GPAICR 0xB4013804
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-#endif /* defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR) */
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-
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-#if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR)
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-void cstm_mips_ixx_set_vpp(struct map_info *map,int vpp)
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-{
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- static DEFINE_SPINLOCK(vpp_lock);
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- static int vpp_count = 0;
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- unsigned long flags;
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-
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- spin_lock_irqsave(&vpp_lock, flags);
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-
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- if (vpp) {
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- if (!vpp_count++) {
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- __u16 data;
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- __u8 data1;
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- static u8 first = 1;
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-
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- // Set GPIO port B pin3 to high
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- data = *(__u16 *)(CC_GPBCR);
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- data = (data & 0xff0f) | 0x0040;
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- *(__u16 *)CC_GPBCR = data;
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- *(__u8 *)CC_GPBDR = (*(__u8*)CC_GPBDR) | 0x08;
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- if (first) {
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- first = 0;
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- /* need to have this delay for first
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- enabling vpp after powerup */
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- udelay(40);
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- }
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- }
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- } else {
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- if (!--vpp_count) {
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- __u16 data;
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-
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- // Set GPIO port B pin3 to high
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- data = *(__u16 *)(CC_GPBCR);
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- data = (data & 0xff3f) | 0x0040;
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- *(__u16 *)CC_GPBCR = data;
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- *(__u8 *)CC_GPBDR = (*(__u8*)CC_GPBDR) & 0xf7;
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- }
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- }
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- spin_unlock_irqrestore(&vpp_lock, flags);
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-}
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-#endif
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-
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/* board and partition description */
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#define MAX_PHYSMAP_PARTITIONS 8
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@@ -107,29 +51,6 @@ struct cstm_mips_ixx_info {
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int num_partitions;
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};
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-#if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR)
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-#define PHYSMAP_NUMBER 1 // number of board desc structs needed, one per contiguous flash type
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-const struct cstm_mips_ixx_info cstm_mips_ixx_board_desc[PHYSMAP_NUMBER] =
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-{
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- { // 28F128J3A in 2x16 configuration
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- "big flash", // name
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- 0x08000000, // window_addr
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- 0x02000000, // window_size
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- 4, // bankwidth
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- 1, // num_partitions
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- }
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-
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-};
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-static struct mtd_partition cstm_mips_ixx_partitions[PHYSMAP_NUMBER][MAX_PHYSMAP_PARTITIONS] = {
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-{ // 28F128J3A in 2x16 configuration
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- {
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- .name = "main partition ",
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- .size = 0x02000000, // 128 x 2 x 128k byte sectors
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- .offset = 0,
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- },
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-},
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-};
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-#else /* defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR) */
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#define PHYSMAP_NUMBER 1 // number of board desc structs needed, one per contiguous flash type
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const struct cstm_mips_ixx_info cstm_mips_ixx_board_desc[PHYSMAP_NUMBER] =
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{
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@@ -151,7 +72,6 @@ static struct mtd_partition cstm_mips_ixx_partitions[PHYSMAP_NUMBER][MAX_PHYSMAP
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},
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},
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};
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-#endif /* defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR) */
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struct map_info cstm_mips_ixx_map[PHYSMAP_NUMBER];
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@@ -184,17 +104,10 @@ int __init init_cstm_mips_ixx(void)
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cstm_mips_ixx_map[i].name = cstm_mips_ixx_board_desc[i].name;
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cstm_mips_ixx_map[i].size = cstm_mips_ixx_board_desc[i].window_size;
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cstm_mips_ixx_map[i].bankwidth = cstm_mips_ixx_board_desc[i].bankwidth;
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-#if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR)
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- cstm_mips_ixx_map[i].set_vpp = cstm_mips_ixx_set_vpp;
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-#endif
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simple_map_init(&cstm_mips_ixx_map[i]);
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//printk(KERN_NOTICE "cstm_mips_ixx: ioremap is %x\n",(unsigned int)(cstm_mips_ixx_map[i].virt));
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}
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-#if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR)
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- setup_ITE_IVR_flash();
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-#endif /* defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR) */
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-
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for (i=0;i<PHYSMAP_NUMBER;i++) {
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parts = &cstm_mips_ixx_partitions[i][0];
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jedec = 0;
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@@ -241,38 +154,6 @@ static void __exit cleanup_cstm_mips_ixx(void)
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}
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}
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}
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-#if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR)
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-void PCISetULongByOffset(__u32 DevNumber, __u32 FuncNumber, __u32 Offset, __u32 data)
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-{
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- __u32 offset;
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-
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- offset = ( unsigned long )( 0x80000000 | ( DevNumber << 11 ) + ( FuncNumber << 8 ) + Offset) ;
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-
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- *(__u32 *)CC_CONFADDR = offset;
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- *(__u32 *)CC_CONFDATA = data;
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-}
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-void setup_ITE_IVR_flash()
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-{
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- __u32 size, base;
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-
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- size = 0x0e000000; // 32MiB
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- base = (0x08000000) >> 8 >>1; // Bug: we must shift one more bit
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-
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- /* need to set ITE flash to 32 bits instead of default 8 */
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-#ifdef CONFIG_MIPS_IVR
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- *(__u32 *)CC_FC_FCR = 0x55;
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- *(__u32 *)CC_GPACR = 0xfffc;
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-#else
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- *(__u32 *)CC_FC_FCR = 0x77;
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-#endif
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- /* turn bursting off */
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- *(__u32 *)CC_FC_DCR = 0x0;
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-
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- /* setup for one chip 4 byte PCI access */
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- PCISetULongByOffset(CC_M68K_DEVICE, CC_M68K_FUNCTION, 0x60, size | base);
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- PCISetULongByOffset(CC_M68K_DEVICE, CC_M68K_FUNCTION, 0x64, 0x02);
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-}
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-#endif /* defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_IVR) */
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module_init(init_cstm_mips_ixx);
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module_exit(cleanup_cstm_mips_ixx);
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@@ -280,4 +161,4 @@ module_exit(cleanup_cstm_mips_ixx);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Alice Hennessy <ahennessy@mvista.com>");
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-MODULE_DESCRIPTION("MTD map driver for ITE 8172G and Globespan IVR boards");
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+MODULE_DESCRIPTION("MTD map driver for MIPS boards");
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