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@@ -906,3 +906,49 @@ void prealloc_protection_domains(void)
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}
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}
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+static struct dma_mapping_ops amd_iommu_dma_ops = {
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+ .alloc_coherent = alloc_coherent,
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+ .free_coherent = free_coherent,
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+ .map_single = map_single,
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+ .unmap_single = unmap_single,
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+ .map_sg = map_sg,
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+ .unmap_sg = unmap_sg,
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+};
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+
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+int __init amd_iommu_init_dma_ops(void)
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+{
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+ struct amd_iommu *iommu;
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+ int order = amd_iommu_aperture_order;
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+ int ret;
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+
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+ list_for_each_entry(iommu, &amd_iommu_list, list) {
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+ iommu->default_dom = dma_ops_domain_alloc(iommu, order);
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+ if (iommu->default_dom == NULL)
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+ return -ENOMEM;
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+ ret = iommu_init_unity_mappings(iommu);
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+ if (ret)
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+ goto free_domains;
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+ }
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+
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+ if (amd_iommu_isolate)
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+ prealloc_protection_domains();
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+
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+ iommu_detected = 1;
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+ force_iommu = 1;
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+ bad_dma_address = 0;
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+ gart_iommu_aperture_disabled = 1;
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+ gart_iommu_aperture = 0;
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+
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+ dma_ops = &amd_iommu_dma_ops;
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+
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+ return 0;
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+
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+free_domains:
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+
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+ list_for_each_entry(iommu, &amd_iommu_list, list) {
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+ if (iommu->default_dom)
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+ dma_ops_domain_free(iommu->default_dom);
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+ }
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+
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+ return ret;
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+}
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