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@@ -21,6 +21,7 @@
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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+#include <mach/gpio.h>
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#define GPIO_BASE(x) IO_ADDRESS(GEMINI_GPIO_BASE(x))
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@@ -44,7 +45,7 @@
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#define GPIO_PORT_NUM 3
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-static void _set_gpio_irqenable(unsigned int base, unsigned int index,
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+static void _set_gpio_irqenable(void __iomem *base, unsigned int index,
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int enable)
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{
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unsigned int reg;
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@@ -57,7 +58,7 @@ static void _set_gpio_irqenable(unsigned int base, unsigned int index,
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static void gpio_ack_irq(struct irq_data *d)
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{
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unsigned int gpio = irq_to_gpio(d->irq);
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- unsigned int base = GPIO_BASE(gpio / 32);
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+ void __iomem *base = GPIO_BASE(gpio / 32);
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__raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR);
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}
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@@ -65,7 +66,7 @@ static void gpio_ack_irq(struct irq_data *d)
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static void gpio_mask_irq(struct irq_data *d)
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{
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unsigned int gpio = irq_to_gpio(d->irq);
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- unsigned int base = GPIO_BASE(gpio / 32);
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+ void __iomem *base = GPIO_BASE(gpio / 32);
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_set_gpio_irqenable(base, gpio % 32, 0);
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}
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@@ -73,7 +74,7 @@ static void gpio_mask_irq(struct irq_data *d)
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static void gpio_unmask_irq(struct irq_data *d)
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{
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unsigned int gpio = irq_to_gpio(d->irq);
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- unsigned int base = GPIO_BASE(gpio / 32);
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+ void __iomem *base = GPIO_BASE(gpio / 32);
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_set_gpio_irqenable(base, gpio % 32, 1);
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}
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@@ -82,7 +83,7 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type)
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{
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unsigned int gpio = irq_to_gpio(d->irq);
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unsigned int gpio_mask = 1 << (gpio % 32);
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- unsigned int base = GPIO_BASE(gpio / 32);
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+ void __iomem *base = GPIO_BASE(gpio / 32);
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unsigned int reg_both, reg_level, reg_type;
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reg_type = __raw_readl(base + GPIO_INT_TYPE);
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@@ -120,7 +121,7 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type)
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__raw_writel(reg_level, base + GPIO_INT_LEVEL);
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__raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE);
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- gpio_ack_irq(d->irq);
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+ gpio_ack_irq(d);
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return 0;
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}
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@@ -153,7 +154,7 @@ static struct irq_chip gpio_irq_chip = {
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static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
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int dir)
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{
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- unsigned int base = GPIO_BASE(offset / 32);
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+ void __iomem *base = GPIO_BASE(offset / 32);
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unsigned int reg;
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reg = __raw_readl(base + GPIO_DIR);
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@@ -166,7 +167,7 @@ static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
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static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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- unsigned int base = GPIO_BASE(offset / 32);
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+ void __iomem *base = GPIO_BASE(offset / 32);
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if (value)
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__raw_writel(1 << (offset % 32), base + GPIO_DATA_SET);
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@@ -176,7 +177,7 @@ static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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static int gemini_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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- unsigned int base = GPIO_BASE(offset / 32);
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+ void __iomem *base = GPIO_BASE(offset / 32);
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return (__raw_readl(base + GPIO_DATA_IN) >> (offset % 32)) & 1;
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}
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