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@@ -396,11 +396,22 @@ clear_err:
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* Wait for bus to IDLE before clearing NAK.
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* If we clear the NAK while bus is still active, then it will stay
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* active and the next transaction may fail.
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+ *
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+ * If no ACK is received during the address phase of a transaction, the
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+ * adapter must report -ENXIO. It is not clear what to return if no ACK
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+ * is received at other times. But we have to be careful to not return
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+ * spurious -ENXIO because that will prevent i2c and drm edid functions
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+ * from retrying. So return -ENXIO only when gmbus properly quiescents -
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+ * timing out seems to happen when there _is_ a ddc chip present, but
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+ * it's slow responding and only answers on the 2nd retry.
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*/
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+ ret = -ENXIO;
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if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
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- 10))
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+ 10)) {
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DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
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adapter->name);
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+ ret = -ETIMEDOUT;
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+ }
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/* Toggle the Software Clear Interrupt bit. This has the effect
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* of resetting the GMBUS controller and so clearing the
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@@ -414,14 +425,6 @@ clear_err:
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adapter->name, msgs[i].addr,
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(msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
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- /*
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- * If no ACK is received during the address phase of a transaction,
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- * the adapter must report -ENXIO.
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- * It is not clear what to return if no ACK is received at other times.
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- * So, we always return -ENXIO in all NAK cases, to ensure we send
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- * it at least during the one case that is specified.
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- */
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- ret = -ENXIO;
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goto out;
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timeout:
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