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@@ -69,9 +69,9 @@ int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
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data->set_baseclock = 0;
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data->set_mclk = 0;
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- clk_disable(data->clk_cdev1);
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- clk_disable(data->clk_pll_a_out0);
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- clk_disable(data->clk_pll_a);
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+ clk_disable_unprepare(data->clk_cdev1);
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+ clk_disable_unprepare(data->clk_pll_a_out0);
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+ clk_disable_unprepare(data->clk_pll_a);
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err = clk_set_rate(data->clk_pll_a, new_baseclock);
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if (err) {
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@@ -87,19 +87,19 @@ int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
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/* Don't set cdev1/extern1 rate; it's locked to pll_a_out0 */
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- err = clk_enable(data->clk_pll_a);
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+ err = clk_prepare_enable(data->clk_pll_a);
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if (err) {
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dev_err(data->dev, "Can't enable pll_a: %d\n", err);
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return err;
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}
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- err = clk_enable(data->clk_pll_a_out0);
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+ err = clk_prepare_enable(data->clk_pll_a_out0);
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if (err) {
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dev_err(data->dev, "Can't enable pll_a_out0: %d\n", err);
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return err;
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}
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- err = clk_enable(data->clk_cdev1);
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+ err = clk_prepare_enable(data->clk_cdev1);
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if (err) {
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dev_err(data->dev, "Can't enable cdev1: %d\n", err);
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return err;
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