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@@ -37,6 +37,7 @@
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#define MSR_NEHALEM_PLATFORM_INFO 0xCE
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#define MSR_NEHALEM_TURBO_RATIO_LIMIT 0x1AD
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+#define MSR_IVT_TURBO_RATIO_LIMIT 0x1AE
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#define MSR_APERF 0xE8
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#define MSR_MPERF 0xE7
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#define MSR_PKG_C2_RESIDENCY 0x60D /* SNB only */
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@@ -61,6 +62,7 @@ unsigned int genuine_intel;
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unsigned int has_invariant_tsc;
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unsigned int do_nehalem_platform_info;
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unsigned int do_nehalem_turbo_ratio_limit;
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+unsigned int do_ivt_turbo_ratio_limit;
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unsigned int extra_msr_offset;
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double bclk;
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unsigned int show_pkg;
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@@ -676,6 +678,9 @@ void print_verbose_header(void)
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get_msr(0, MSR_NEHALEM_PLATFORM_INFO, &msr);
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+ if (verbose > 1)
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+ fprintf(stderr, "MSR_NEHALEM_PLATFORM_INFO: 0x%llx\n", msr);
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+
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ratio = (msr >> 40) & 0xFF;
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fprintf(stderr, "%d * %.0f = %.0f MHz max efficiency\n",
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ratio, bclk, ratio * bclk);
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@@ -684,14 +689,84 @@ void print_verbose_header(void)
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fprintf(stderr, "%d * %.0f = %.0f MHz TSC frequency\n",
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ratio, bclk, ratio * bclk);
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+ if (!do_ivt_turbo_ratio_limit)
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+ goto print_nhm_turbo_ratio_limits;
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+
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+ get_msr(0, MSR_IVT_TURBO_RATIO_LIMIT, &msr);
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+
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if (verbose > 1)
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- fprintf(stderr, "MSR_NEHALEM_PLATFORM_INFO: 0x%llx\n", msr);
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+ fprintf(stderr, "MSR_IVT_TURBO_RATIO_LIMIT: 0x%llx\n", msr);
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+
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+ ratio = (msr >> 56) & 0xFF;
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+ if (ratio)
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+ fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 16 active cores\n",
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+ ratio, bclk, ratio * bclk);
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+
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+ ratio = (msr >> 48) & 0xFF;
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+ if (ratio)
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+ fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 15 active cores\n",
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+ ratio, bclk, ratio * bclk);
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+
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+ ratio = (msr >> 40) & 0xFF;
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+ if (ratio)
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+ fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 14 active cores\n",
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+ ratio, bclk, ratio * bclk);
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+
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+ ratio = (msr >> 32) & 0xFF;
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+ if (ratio)
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+ fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 13 active cores\n",
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+ ratio, bclk, ratio * bclk);
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+
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+ ratio = (msr >> 24) & 0xFF;
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+ if (ratio)
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+ fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 12 active cores\n",
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+ ratio, bclk, ratio * bclk);
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+
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+ ratio = (msr >> 16) & 0xFF;
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+ if (ratio)
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+ fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 11 active cores\n",
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+ ratio, bclk, ratio * bclk);
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+
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+ ratio = (msr >> 8) & 0xFF;
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+ if (ratio)
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+ fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 10 active cores\n",
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+ ratio, bclk, ratio * bclk);
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+
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+ ratio = (msr >> 0) & 0xFF;
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+ if (ratio)
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+ fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 9 active cores\n",
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+ ratio, bclk, ratio * bclk);
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+
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+print_nhm_turbo_ratio_limits:
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if (!do_nehalem_turbo_ratio_limit)
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return;
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get_msr(0, MSR_NEHALEM_TURBO_RATIO_LIMIT, &msr);
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+ if (verbose > 1)
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+ fprintf(stderr, "MSR_NEHALEM_TURBO_RATIO_LIMIT: 0x%llx\n", msr);
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+
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+ ratio = (msr >> 56) & 0xFF;
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+ if (ratio)
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+ fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 8 active cores\n",
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+ ratio, bclk, ratio * bclk);
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+
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+ ratio = (msr >> 48) & 0xFF;
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+ if (ratio)
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+ fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 7 active cores\n",
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+ ratio, bclk, ratio * bclk);
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+
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+ ratio = (msr >> 40) & 0xFF;
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+ if (ratio)
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+ fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 6 active cores\n",
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+ ratio, bclk, ratio * bclk);
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+
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+ ratio = (msr >> 32) & 0xFF;
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+ if (ratio)
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+ fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 5 active cores\n",
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+ ratio, bclk, ratio * bclk);
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+
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ratio = (msr >> 24) & 0xFF;
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if (ratio)
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fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 4 active cores\n",
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@@ -711,7 +786,6 @@ void print_verbose_header(void)
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if (ratio)
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fprintf(stderr, "%d * %.0f = %.0f MHz max turbo 1 active cores\n",
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ratio, bclk, ratio * bclk);
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-
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}
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void free_all_buffers(void)
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@@ -1045,6 +1119,22 @@ int has_nehalem_turbo_ratio_limit(unsigned int family, unsigned int model)
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return 0;
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}
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}
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+int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model)
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+{
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+ if (!genuine_intel)
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+ return 0;
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+
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+ if (family != 6)
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+ return 0;
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+
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+ switch (model) {
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+ case 0x3E: /* IVB Xeon */
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+ return 1;
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+ default:
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+ return 0;
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+ }
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+}
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+
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int is_snb(unsigned int family, unsigned int model)
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{
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@@ -1144,6 +1234,7 @@ void check_cpuid()
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bclk = discover_bclk(family, model);
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do_nehalem_turbo_ratio_limit = has_nehalem_turbo_ratio_limit(family, model);
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+ do_ivt_turbo_ratio_limit = has_ivt_turbo_ratio_limit(family, model);
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}
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