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@@ -23,6 +23,7 @@
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#include <asm/cacheflush.h>
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#include <asm/hardware/cache-l2x0.h>
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+#include <asm/smp_scu.h>
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#include <plat/cpu.h>
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#include <plat/pm.h>
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@@ -213,27 +214,6 @@ static int exynos4_pm_add(struct sys_device *sysdev)
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return 0;
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}
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-/* This function copy from linux/arch/arm/kernel/smp_scu.c */
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-
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-void exynos4_scu_enable(void __iomem *scu_base)
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-{
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- u32 scu_ctrl;
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-
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- scu_ctrl = __raw_readl(scu_base);
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- /* already enabled? */
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- if (scu_ctrl & 1)
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- return;
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-
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- scu_ctrl |= 1;
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- __raw_writel(scu_ctrl, scu_base);
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-
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- /*
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- * Ensure that the data accessed by CPU0 before the SCU was
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- * initialised is visible to the other CPUs.
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- */
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- flush_cache_all();
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-}
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-
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static unsigned long pll_base_rate;
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static void exynos4_restore_pll(void)
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@@ -402,7 +382,7 @@ static void exynos4_pm_resume(void)
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exynos4_restore_pll();
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- exynos4_scu_enable(S5P_VA_SCU);
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+ scu_enable(S5P_VA_SCU);
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#ifdef CONFIG_CACHE_L2X0
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s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
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