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@@ -67,8 +67,8 @@
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#define DRV_MODULE_NAME "tg3"
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#define PFX DRV_MODULE_NAME ": "
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-#define DRV_MODULE_VERSION "3.40"
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-#define DRV_MODULE_RELDATE "September 15, 2005"
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+#define DRV_MODULE_VERSION "3.41"
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+#define DRV_MODULE_RELDATE "September 27, 2005"
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#define TG3_DEF_MAC_MODE 0
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#define TG3_DEF_RX_MODE 0
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@@ -3389,7 +3389,8 @@ static irqreturn_t tg3_test_isr(int irq, void *dev_id,
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struct tg3 *tp = netdev_priv(dev);
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struct tg3_hw_status *sblk = tp->hw_status;
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- if (sblk->status & SD_STATUS_UPDATED) {
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+ if ((sblk->status & SD_STATUS_UPDATED) ||
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+ !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
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tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
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0x00000001);
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return IRQ_RETVAL(1);
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@@ -5395,6 +5396,9 @@ static int tg3_set_mac_addr(struct net_device *dev, void *p)
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struct tg3 *tp = netdev_priv(dev);
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struct sockaddr *addr = p;
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+ if (!is_valid_ether_addr(addr->sa_data))
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+ return -EINVAL;
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+
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memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
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spin_lock_bh(&tp->lock);
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@@ -5806,6 +5810,13 @@ static int tg3_reset_hw(struct tg3 *tp)
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}
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memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
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+ if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
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+ tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
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+ /* reset to prevent losing 1st rx packet intermittently */
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+ tw32_f(MAC_RX_MODE, RX_MODE_RESET);
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+ udelay(10);
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+ }
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+
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tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
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MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
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tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
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@@ -5937,7 +5948,7 @@ static int tg3_reset_hw(struct tg3 *tp)
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tw32(MAC_LED_CTRL, tp->led_ctrl);
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tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
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- if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
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+ if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
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tw32_f(MAC_RX_MODE, RX_MODE_RESET);
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udelay(10);
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}
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@@ -7360,12 +7371,17 @@ static int tg3_nway_reset(struct net_device *dev)
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if (!netif_running(dev))
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return -EAGAIN;
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+ if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
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+ return -EINVAL;
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+
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spin_lock_bh(&tp->lock);
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r = -EINVAL;
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tg3_readphy(tp, MII_BMCR, &bmcr);
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if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
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- (bmcr & BMCR_ANENABLE)) {
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- tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART);
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+ ((bmcr & BMCR_ANENABLE) ||
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+ (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
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+ tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
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+ BMCR_ANENABLE);
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r = 0;
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}
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spin_unlock_bh(&tp->lock);
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@@ -7927,19 +7943,32 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
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struct tg3_rx_buffer_desc *desc;
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if (loopback_mode == TG3_MAC_LOOPBACK) {
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+ /* HW errata - mac loopback fails in some cases on 5780.
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+ * Normal traffic and PHY loopback are not affected by
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+ * errata.
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+ */
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+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
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+ return 0;
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+
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mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
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MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
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MAC_MODE_PORT_MODE_GMII;
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tw32(MAC_MODE, mac_mode);
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} else if (loopback_mode == TG3_PHY_LOOPBACK) {
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+ tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
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+ BMCR_SPEED1000);
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+ udelay(40);
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+ /* reset to prevent losing 1st rx packet intermittently */
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+ if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
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+ tw32_f(MAC_RX_MODE, RX_MODE_RESET);
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+ udelay(10);
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+ tw32_f(MAC_RX_MODE, tp->rx_mode);
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+ }
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mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
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MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII;
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if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
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mac_mode &= ~MAC_MODE_LINK_POLARITY;
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tw32(MAC_MODE, mac_mode);
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-
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- tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
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- BMCR_SPEED1000);
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}
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else
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return -EINVAL;
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@@ -10324,6 +10353,44 @@ static char * __devinit tg3_phy_string(struct tg3 *tp)
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};
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}
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+static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
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+{
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+ if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
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+ strcpy(str, "PCI Express");
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+ return str;
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+ } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
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+ u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
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+
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+ strcpy(str, "PCIX:");
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+
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+ if ((clock_ctrl == 7) ||
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+ ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
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+ GRC_MISC_CFG_BOARD_ID_5704CIOBE))
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+ strcat(str, "133MHz");
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+ else if (clock_ctrl == 0)
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+ strcat(str, "33MHz");
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+ else if (clock_ctrl == 2)
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+ strcat(str, "50MHz");
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+ else if (clock_ctrl == 4)
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+ strcat(str, "66MHz");
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+ else if (clock_ctrl == 6)
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+ strcat(str, "100MHz");
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+ else if (clock_ctrl == 7)
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+ strcat(str, "133MHz");
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+ } else {
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+ strcpy(str, "PCI:");
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+ if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
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+ strcat(str, "66MHz");
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+ else
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+ strcat(str, "33MHz");
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+ }
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+ if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
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+ strcat(str, ":32-bit");
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+ else
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+ strcat(str, ":64-bit");
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+ return str;
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+}
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+
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static struct pci_dev * __devinit tg3_find_5704_peer(struct tg3 *tp)
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{
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struct pci_dev *peer;
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@@ -10386,6 +10453,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
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struct net_device *dev;
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struct tg3 *tp;
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int i, err, pci_using_dac, pm_cap;
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+ char str[40];
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if (tg3_version_printed++ == 0)
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printk(KERN_INFO "%s", version);
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@@ -10631,16 +10699,12 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
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pci_set_drvdata(pdev, dev);
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- printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (PCI%s:%s:%s) %sBaseT Ethernet ",
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+ printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %sBaseT Ethernet ",
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dev->name,
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tp->board_part_number,
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tp->pci_chip_rev_id,
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tg3_phy_string(tp),
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- ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
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- ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
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- ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
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- ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
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- ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"),
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+ tg3_bus_string(tp, str),
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(tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
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for (i = 0; i < 6; i++)
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