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@@ -4939,39 +4939,15 @@ static int ipr_eh_abort(struct scsi_cmnd * scsi_cmd)
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/**
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* ipr_handle_other_interrupt - Handle "other" interrupts
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* @ioa_cfg: ioa config struct
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+ * @int_reg: interrupt register
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*
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* Return value:
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* IRQ_NONE / IRQ_HANDLED
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**/
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-static irqreturn_t ipr_handle_other_interrupt(struct ipr_ioa_cfg *ioa_cfg)
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+static irqreturn_t ipr_handle_other_interrupt(struct ipr_ioa_cfg *ioa_cfg,
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+ volatile u32 int_reg)
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{
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irqreturn_t rc = IRQ_HANDLED;
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- volatile u32 int_reg, int_mask_reg;
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-
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- int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg32);
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- int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32) & ~int_mask_reg;
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-
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- /* If an interrupt on the adapter did not occur, ignore it.
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- * Or in the case of SIS 64, check for a stage change interrupt.
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- */
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- if ((int_reg & IPR_PCII_OPER_INTERRUPTS) == 0) {
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- if (ioa_cfg->sis64) {
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- int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
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- int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg;
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- if (int_reg & IPR_PCII_IPL_STAGE_CHANGE) {
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-
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- /* clear stage change */
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- writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.clr_interrupt_reg);
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- int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg;
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- list_del(&ioa_cfg->reset_cmd->queue);
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- del_timer(&ioa_cfg->reset_cmd->timer);
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- ipr_reset_ioa_job(ioa_cfg->reset_cmd);
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- return IRQ_HANDLED;
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- }
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- }
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-
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- return IRQ_NONE;
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- }
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if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) {
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/* Mask the interrupt */
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@@ -5032,7 +5008,7 @@ static irqreturn_t ipr_isr(int irq, void *devp)
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{
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struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)devp;
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unsigned long lock_flags = 0;
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- volatile u32 int_reg;
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+ volatile u32 int_reg, int_mask_reg;
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u32 ioasc;
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u16 cmd_index;
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int num_hrrq = 0;
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@@ -5047,6 +5023,33 @@ static irqreturn_t ipr_isr(int irq, void *devp)
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return IRQ_NONE;
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}
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+ int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg32);
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+ int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32) & ~int_mask_reg;
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+
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+ /* If an interrupt on the adapter did not occur, ignore it.
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+ * Or in the case of SIS 64, check for a stage change interrupt.
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+ */
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+ if (unlikely((int_reg & IPR_PCII_OPER_INTERRUPTS) == 0)) {
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+ if (ioa_cfg->sis64) {
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+ int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
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+ int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg;
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+ if (int_reg & IPR_PCII_IPL_STAGE_CHANGE) {
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+
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+ /* clear stage change */
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+ writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.clr_interrupt_reg);
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+ int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg;
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+ list_del(&ioa_cfg->reset_cmd->queue);
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+ del_timer(&ioa_cfg->reset_cmd->timer);
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+ ipr_reset_ioa_job(ioa_cfg->reset_cmd);
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+ spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
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+ return IRQ_HANDLED;
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+ }
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+ }
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+
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+ spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
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+ return IRQ_NONE;
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+ }
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+
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while (1) {
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ipr_cmd = NULL;
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@@ -5086,7 +5089,7 @@ static irqreturn_t ipr_isr(int irq, void *devp)
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/* Clear the PCI interrupt */
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do {
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writel(IPR_PCII_HRRQ_UPDATED, ioa_cfg->regs.clr_interrupt_reg32);
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- int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
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+ int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32) & ~int_mask_reg;
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} while (int_reg & IPR_PCII_HRRQ_UPDATED &&
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num_hrrq++ < IPR_MAX_HRRQ_RETRIES);
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@@ -5101,7 +5104,7 @@ static irqreturn_t ipr_isr(int irq, void *devp)
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}
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if (unlikely(rc == IRQ_NONE))
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- rc = ipr_handle_other_interrupt(ioa_cfg);
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+ rc = ipr_handle_other_interrupt(ioa_cfg, int_reg);
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spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
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return rc;
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