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@@ -0,0 +1,879 @@
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+/* IO interface mux allocator for ETRAX100LX.
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+ * Copyright 2004, Axis Communications AB
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+ * $Id: io_interface_mux.c,v 1.2 2004/12/21 12:08:38 starvik Exp $
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+ */
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+
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+
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+/* C.f. ETRAX100LX Designer's Reference 20.9 */
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+
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+#include <linux/kernel.h>
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+#include <linux/slab.h>
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+#include <linux/errno.h>
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+#include <linux/module.h>
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+#include <linux/init.h>
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+
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+#include <asm/arch/svinto.h>
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+#include <asm/io.h>
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+#include <asm/arch/io_interface_mux.h>
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+
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+
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+#define DBG(s)
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+
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+/* Macro to access ETRAX 100 registers */
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+#define SETS(var, reg, field, val) var = (var & ~IO_MASK_(reg##_, field##_)) | \
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+ IO_STATE_(reg##_, field##_, _##val)
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+
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+enum io_if_group {
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+ group_a = (1<<0),
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+ group_b = (1<<1),
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+ group_c = (1<<2),
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+ group_d = (1<<3),
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+ group_e = (1<<4),
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+ group_f = (1<<5)
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+};
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+
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+struct watcher
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+{
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+ void (*notify)(const unsigned int gpio_in_available,
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+ const unsigned int gpio_out_available,
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+ const unsigned char pa_available,
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+ const unsigned char pb_available);
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+ struct watcher *next;
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+};
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+
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+
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+struct if_group
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+{
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+ enum io_if_group group;
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+ unsigned char used;
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+ enum cris_io_interface owner;
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+};
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+
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+
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+struct interface
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+{
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+ enum cris_io_interface ioif;
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+ unsigned char groups;
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+ unsigned char used;
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+ char *owner;
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+ unsigned int gpio_g_in;
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+ unsigned int gpio_g_out;
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+ unsigned char gpio_b;
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+};
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+
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+static struct if_group if_groups[6] = {
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+ {
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+ .group = group_a,
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+ .used = 0,
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+ },
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+ {
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+ .group = group_b,
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+ .used = 0,
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+ },
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+ {
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+ .group = group_c,
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+ .used = 0,
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+ },
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+ {
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+ .group = group_d,
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+ .used = 0,
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+ },
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+ {
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+ .group = group_e,
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+ .used = 0,
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+ },
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+ {
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+ .group = group_f,
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+ .used = 0,
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+ }
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+};
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+
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+/* The order in the array must match the order of enum
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+ * cris_io_interface in io_interface_mux.h */
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+static struct interface interfaces[] = {
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+ /* Begin Non-multiplexed interfaces */
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+ {
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+ .ioif = if_eth,
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+ .groups = 0,
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+ .gpio_g_in = 0,
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+ .gpio_g_out = 0,
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+ .gpio_b = 0
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+ },
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+ {
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+ .ioif = if_serial_0,
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+ .groups = 0,
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+ .gpio_g_in = 0,
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+ .gpio_g_out = 0,
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+ .gpio_b = 0
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+ },
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+ /* End Non-multiplexed interfaces */
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+ {
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+ .ioif = if_serial_1,
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+ .groups = group_e,
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+ .gpio_g_in = 0x00000000,
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+ .gpio_g_out = 0x00000000,
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+ .gpio_b = 0x00
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+ },
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+ {
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+ .ioif = if_serial_2,
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+ .groups = group_b,
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+ .gpio_g_in = 0x000000c0,
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+ .gpio_g_out = 0x000000c0,
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+ .gpio_b = 0x00
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+ },
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+ {
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+ .ioif = if_serial_3,
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+ .groups = group_c,
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+ .gpio_g_in = 0xc0000000,
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+ .gpio_g_out = 0xc0000000,
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+ .gpio_b = 0x00
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+ },
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+ {
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+ .ioif = if_sync_serial_1,
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+ .groups = group_e | group_f, /* if_sync_serial_1 and if_sync_serial_3
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+ can be used simultaneously */
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+ .gpio_g_in = 0x00000000,
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+ .gpio_g_out = 0x00000000,
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+ .gpio_b = 0x10
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+ },
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+ {
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+ .ioif = if_sync_serial_3,
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+ .groups = group_c | group_f,
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+ .gpio_g_in = 0xc0000000,
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+ .gpio_g_out = 0xc0000000,
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+ .gpio_b = 0x80
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+ },
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+ {
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+ .ioif = if_shared_ram,
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+ .groups = group_a,
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+ .gpio_g_in = 0x0000ff3e,
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+ .gpio_g_out = 0x0000ff38,
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+ .gpio_b = 0x00
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+ },
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+ {
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+ .ioif = if_shared_ram_w,
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+ .groups = group_a | group_d,
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+ .gpio_g_in = 0x00ffff3e,
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+ .gpio_g_out = 0x00ffff38,
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+ .gpio_b = 0x00
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+ },
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+ {
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+ .ioif = if_par_0,
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+ .groups = group_a,
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+ .gpio_g_in = 0x0000ff3e,
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+ .gpio_g_out = 0x0000ff3e,
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+ .gpio_b = 0x00
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+ },
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+ {
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+ .ioif = if_par_1,
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+ .groups = group_d,
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+ .gpio_g_in = 0x3eff0000,
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+ .gpio_g_out = 0x3eff0000,
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+ .gpio_b = 0x00
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+ },
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+ {
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+ .ioif = if_par_w,
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+ .groups = group_a | group_d,
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+ .gpio_g_in = 0x00ffff3e,
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+ .gpio_g_out = 0x00ffff3e,
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+ .gpio_b = 0x00
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+ },
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+ {
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+ .ioif = if_scsi8_0,
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+ .groups = group_a | group_b | group_f, /* if_scsi8_0 and if_scsi8_1
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+ can be used simultaneously */
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+ .gpio_g_in = 0x0000ffff,
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+ .gpio_g_out = 0x0000ffff,
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+ .gpio_b = 0x10
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+ },
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+ {
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+ .ioif = if_scsi8_1,
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+ .groups = group_c | group_d | group_f, /* if_scsi8_0 and if_scsi8_1
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+ can be used simultaneously */
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+ .gpio_g_in = 0xffff0000,
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+ .gpio_g_out = 0xffff0000,
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+ .gpio_b = 0x80
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+ },
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+ {
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+ .ioif = if_scsi_w,
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+ .groups = group_a | group_b | group_d | group_f,
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+ .gpio_g_in = 0x01ffffff,
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+ .gpio_g_out = 0x07ffffff,
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+ .gpio_b = 0x80
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+ },
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+ {
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+ .ioif = if_ata,
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+ .groups = group_a | group_b | group_c | group_d,
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+ .gpio_g_in = 0xf9ffffff,
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+ .gpio_g_out = 0xffffffff,
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+ .gpio_b = 0x80
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+ },
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+ {
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+ .ioif = if_csp,
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+ .groups = group_f, /* if_csp and if_i2c can be used simultaneously */
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+ .gpio_g_in = 0x00000000,
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+ .gpio_g_out = 0x00000000,
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+ .gpio_b = 0xfc
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+ },
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+ {
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+ .ioif = if_i2c,
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+ .groups = group_f, /* if_csp and if_i2c can be used simultaneously */
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+ .gpio_g_in = 0x00000000,
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+ .gpio_g_out = 0x00000000,
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+ .gpio_b = 0x03
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+ },
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+ {
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+ .ioif = if_usb_1,
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+ .groups = group_e | group_f,
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+ .gpio_g_in = 0x00000000,
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+ .gpio_g_out = 0x00000000,
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+ .gpio_b = 0x2c
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+ },
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+ {
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+ .ioif = if_usb_2,
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+ .groups = group_d,
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+ .gpio_g_in = 0x0e000000,
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+ .gpio_g_out = 0x3c000000,
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+ .gpio_b = 0x00
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+ },
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+ /* GPIO pins */
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+ {
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+ .ioif = if_gpio_grp_a,
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+ .groups = group_a,
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+ .gpio_g_in = 0x0000ff3f,
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+ .gpio_g_out = 0x0000ff3f,
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+ .gpio_b = 0x00
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+ },
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+ {
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+ .ioif = if_gpio_grp_b,
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+ .groups = group_b,
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+ .gpio_g_in = 0x000000c0,
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+ .gpio_g_out = 0x000000c0,
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+ .gpio_b = 0x00
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+ },
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+ {
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+ .ioif = if_gpio_grp_c,
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+ .groups = group_c,
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+ .gpio_g_in = 0xc0000000,
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+ .gpio_g_out = 0xc0000000,
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+ .gpio_b = 0x00
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+ },
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+ {
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+ .ioif = if_gpio_grp_d,
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+ .groups = group_d,
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+ .gpio_g_in = 0x3fff0000,
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+ .gpio_g_out = 0x3fff0000,
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+ .gpio_b = 0x00
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+ },
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+ {
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+ .ioif = if_gpio_grp_e,
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+ .groups = group_e,
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+ .gpio_g_in = 0x00000000,
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+ .gpio_g_out = 0x00000000,
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+ .gpio_b = 0x00
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+ },
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+ {
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+ .ioif = if_gpio_grp_f,
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+ .groups = group_f,
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+ .gpio_g_in = 0x00000000,
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+ .gpio_g_out = 0x00000000,
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+ .gpio_b = 0xff
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+ }
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+ /* Array end */
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+};
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+
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+static struct watcher *watchers = NULL;
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+
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+static unsigned int gpio_in_pins = 0xffffffff;
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+static unsigned int gpio_out_pins = 0xffffffff;
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+static unsigned char gpio_pb_pins = 0xff;
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+static unsigned char gpio_pa_pins = 0xff;
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+
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+static enum cris_io_interface gpio_pa_owners[8];
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+static enum cris_io_interface gpio_pb_owners[8];
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+static enum cris_io_interface gpio_pg_owners[32];
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+
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+static int cris_io_interface_init(void);
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+
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+static unsigned char clear_group_from_set(const unsigned char groups, struct if_group *group)
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+{
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+ return (groups & ~group->group);
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+}
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+
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+
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+static struct if_group *get_group(const unsigned char groups)
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+{
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+ int i;
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+ for (i = 0; i < sizeof(if_groups)/sizeof(struct if_group); i++) {
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+ if (groups & if_groups[i].group) {
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+ return &if_groups[i];
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+ }
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+ }
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+ return NULL;
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+}
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+
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+
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+static void notify_watchers(void)
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+{
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+ struct watcher *w = watchers;
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+
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+ DBG(printk("io_interface_mux: notifying watchers\n"));
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+
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+ while (NULL != w) {
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+ w->notify((const unsigned int)gpio_in_pins,
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+ (const unsigned int)gpio_out_pins,
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+ (const unsigned char)gpio_pa_pins,
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+ (const unsigned char)gpio_pb_pins);
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+ w = w->next;
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+ }
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+}
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+
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+
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+int cris_request_io_interface(enum cris_io_interface ioif, const char *device_id)
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+{
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+ int set_gen_config = 0;
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+ int set_gen_config_ii = 0;
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+ unsigned long int gens;
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+ unsigned long int gens_ii;
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+ struct if_group *grp;
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+ unsigned char group_set;
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+ unsigned long flags;
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+
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+ (void)cris_io_interface_init();
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+
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+ DBG(printk("cris_request_io_interface(%d, \"%s\")\n", ioif, device_id));
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+
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+ if ((ioif >= if_max_interfaces) || (ioif < 0)) {
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+ printk(KERN_CRIT "cris_request_io_interface: Bad interface %u submitted for %s\n",
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+ ioif,
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+ device_id);
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+ return -EINVAL;
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+ }
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+
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+ local_irq_save(flags);
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+
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+ if (interfaces[ioif].used) {
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+ local_irq_restore(flags);
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+ printk(KERN_CRIT "cris_io_interface: Cannot allocate interface for %s, in use by %s\n",
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+ device_id,
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+ interfaces[ioif].owner);
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+ return -EBUSY;
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+ }
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+
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+ /* Check that all required groups are free before allocating, */
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+ group_set = interfaces[ioif].groups;
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+ while (NULL != (grp = get_group(group_set))) {
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+ if (grp->used) {
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+ if (grp->group == group_f) {
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+ if ((if_sync_serial_1 == ioif) ||
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+ (if_sync_serial_3 == ioif)) {
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+ if ((grp->owner != if_sync_serial_1) &&
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+ (grp->owner != if_sync_serial_3)) {
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+ local_irq_restore(flags);
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+ return -EBUSY;
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+ }
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+ } else if ((if_scsi8_0 == ioif) ||
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+ (if_scsi8_1 == ioif)) {
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+ if ((grp->owner != if_scsi8_0) &&
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+ (grp->owner != if_scsi8_1)) {
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+ local_irq_restore(flags);
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+ return -EBUSY;
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+ }
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+ }
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+ } else {
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+ local_irq_restore(flags);
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+ return -EBUSY;
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+ }
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+ }
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+ group_set = clear_group_from_set(group_set, grp);
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+ }
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+
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+ /* Are the required GPIO pins available too? */
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+ if (((interfaces[ioif].gpio_g_in & gpio_in_pins) != interfaces[ioif].gpio_g_in) ||
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+ ((interfaces[ioif].gpio_g_out & gpio_out_pins) != interfaces[ioif].gpio_g_out) ||
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+ ((interfaces[ioif].gpio_b & gpio_pb_pins) != interfaces[ioif].gpio_b)) {
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+ printk(KERN_CRIT "cris_request_io_interface: Could not get required pins for interface %u\n",
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+ ioif);
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+ return -EBUSY;
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+ }
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+
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+ /* All needed I/O pins and pin groups are free, allocate. */
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+ group_set = interfaces[ioif].groups;
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+ while (NULL != (grp = get_group(group_set))) {
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+ grp->used = 1;
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+ grp->owner = ioif;
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+ group_set = clear_group_from_set(group_set, grp);
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+ }
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+
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+ gens = genconfig_shadow;
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+ gens_ii = gen_config_ii_shadow;
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+
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+ set_gen_config = 1;
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+ switch (ioif)
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+ {
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+ /* Begin Non-multiplexed interfaces */
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+ case if_eth:
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+ /* fall through */
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+ case if_serial_0:
|
|
|
+ set_gen_config = 0;
|
|
|
+ break;
|
|
|
+ /* End Non-multiplexed interfaces */
|
|
|
+ case if_serial_1:
|
|
|
+ set_gen_config_ii = 1;
|
|
|
+ SETS(gens_ii, R_GEN_CONFIG_II, sermode1, async);
|
|
|
+ break;
|
|
|
+ case if_serial_2:
|
|
|
+ SETS(gens, R_GEN_CONFIG, ser2, select);
|
|
|
+ break;
|
|
|
+ case if_serial_3:
|
|
|
+ SETS(gens, R_GEN_CONFIG, ser3, select);
|
|
|
+ set_gen_config_ii = 1;
|
|
|
+ SETS(gens_ii, R_GEN_CONFIG_II, sermode3, async);
|
|
|
+ break;
|
|
|
+ case if_sync_serial_1:
|
|
|
+ set_gen_config_ii = 1;
|
|
|
+ SETS(gens_ii, R_GEN_CONFIG_II, sermode1, sync);
|
|
|
+ break;
|
|
|
+ case if_sync_serial_3:
|
|
|
+ SETS(gens, R_GEN_CONFIG, ser3, select);
|
|
|
+ set_gen_config_ii = 1;
|
|
|
+ SETS(gens_ii, R_GEN_CONFIG_II, sermode3, sync);
|
|
|
+ break;
|
|
|
+ case if_shared_ram:
|
|
|
+ SETS(gens, R_GEN_CONFIG, mio, select);
|
|
|
+ break;
|
|
|
+ case if_shared_ram_w:
|
|
|
+ SETS(gens, R_GEN_CONFIG, mio_w, select);
|
|
|
+ break;
|
|
|
+ case if_par_0:
|
|
|
+ SETS(gens, R_GEN_CONFIG, par0, select);
|
|
|
+ break;
|
|
|
+ case if_par_1:
|
|
|
+ SETS(gens, R_GEN_CONFIG, par1, select);
|
|
|
+ break;
|
|
|
+ case if_par_w:
|
|
|
+ SETS(gens, R_GEN_CONFIG, par0, select);
|
|
|
+ SETS(gens, R_GEN_CONFIG, par_w, select);
|
|
|
+ break;
|
|
|
+ case if_scsi8_0:
|
|
|
+ SETS(gens, R_GEN_CONFIG, scsi0, select);
|
|
|
+ break;
|
|
|
+ case if_scsi8_1:
|
|
|
+ SETS(gens, R_GEN_CONFIG, scsi1, select);
|
|
|
+ break;
|
|
|
+ case if_scsi_w:
|
|
|
+ SETS(gens, R_GEN_CONFIG, scsi0, select);
|
|
|
+ SETS(gens, R_GEN_CONFIG, scsi0w, select);
|
|
|
+ break;
|
|
|
+ case if_ata:
|
|
|
+ SETS(gens, R_GEN_CONFIG, ata, select);
|
|
|
+ break;
|
|
|
+ case if_csp:
|
|
|
+ /* fall through */
|
|
|
+ case if_i2c:
|
|
|
+ set_gen_config = 0;
|
|
|
+ break;
|
|
|
+ case if_usb_1:
|
|
|
+ SETS(gens, R_GEN_CONFIG, usb1, select);
|
|
|
+ break;
|
|
|
+ case if_usb_2:
|
|
|
+ SETS(gens, R_GEN_CONFIG, usb2, select);
|
|
|
+ break;
|
|
|
+ case if_gpio_grp_a:
|
|
|
+ /* GPIO groups are only accounted, don't do configuration changes. */
|
|
|
+ /* fall through */
|
|
|
+ case if_gpio_grp_b:
|
|
|
+ /* fall through */
|
|
|
+ case if_gpio_grp_c:
|
|
|
+ /* fall through */
|
|
|
+ case if_gpio_grp_d:
|
|
|
+ /* fall through */
|
|
|
+ case if_gpio_grp_e:
|
|
|
+ /* fall through */
|
|
|
+ case if_gpio_grp_f:
|
|
|
+ set_gen_config = 0;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ panic("cris_request_io_interface: Bad interface %u submitted for %s\n",
|
|
|
+ ioif,
|
|
|
+ device_id);
|
|
|
+ }
|
|
|
+
|
|
|
+ interfaces[ioif].used = 1;
|
|
|
+ interfaces[ioif].owner = (char*)device_id;
|
|
|
+
|
|
|
+ if (set_gen_config) {
|
|
|
+ volatile int i;
|
|
|
+ genconfig_shadow = gens;
|
|
|
+ *R_GEN_CONFIG = genconfig_shadow;
|
|
|
+ /* Wait 12 cycles before doing any DMA command */
|
|
|
+ for(i = 6; i > 0; i--)
|
|
|
+ nop();
|
|
|
+ }
|
|
|
+ if (set_gen_config_ii) {
|
|
|
+ gen_config_ii_shadow = gens_ii;
|
|
|
+ *R_GEN_CONFIG_II = gen_config_ii_shadow;
|
|
|
+ }
|
|
|
+
|
|
|
+ DBG(printk("GPIO pins: available before: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
|
|
|
+ gpio_in_pins, gpio_out_pins, gpio_pb_pins));
|
|
|
+ DBG(printk("grabbing pins: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
|
|
|
+ interfaces[ioif].gpio_g_in,
|
|
|
+ interfaces[ioif].gpio_g_out,
|
|
|
+ interfaces[ioif].gpio_b));
|
|
|
+
|
|
|
+ gpio_in_pins &= ~interfaces[ioif].gpio_g_in;
|
|
|
+ gpio_out_pins &= ~interfaces[ioif].gpio_g_out;
|
|
|
+ gpio_pb_pins &= ~interfaces[ioif].gpio_b;
|
|
|
+
|
|
|
+ DBG(printk("GPIO pins: available after: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
|
|
|
+ gpio_in_pins, gpio_out_pins, gpio_pb_pins));
|
|
|
+
|
|
|
+ local_irq_restore(flags);
|
|
|
+
|
|
|
+ notify_watchers();
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+void cris_free_io_interface(enum cris_io_interface ioif)
|
|
|
+{
|
|
|
+ struct if_group *grp;
|
|
|
+ unsigned char group_set;
|
|
|
+ unsigned long flags;
|
|
|
+
|
|
|
+ (void)cris_io_interface_init();
|
|
|
+
|
|
|
+ if ((ioif >= if_max_interfaces) || (ioif < 0)) {
|
|
|
+ printk(KERN_CRIT "cris_free_io_interface: Bad interface %u\n",
|
|
|
+ ioif);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ local_irq_save(flags);
|
|
|
+ if (!interfaces[ioif].used) {
|
|
|
+ printk(KERN_CRIT "cris_free_io_interface: Freeing free interface %u\n",
|
|
|
+ ioif);
|
|
|
+ local_irq_restore(flags);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ group_set = interfaces[ioif].groups;
|
|
|
+ while (NULL != (grp = get_group(group_set))) {
|
|
|
+ if (grp->group == group_f) {
|
|
|
+ switch (ioif)
|
|
|
+ {
|
|
|
+ case if_sync_serial_1:
|
|
|
+ if ((grp->owner == if_sync_serial_1) &&
|
|
|
+ interfaces[if_sync_serial_3].used) {
|
|
|
+ grp->owner = if_sync_serial_3;
|
|
|
+ } else
|
|
|
+ grp->used = 0;
|
|
|
+ break;
|
|
|
+ case if_sync_serial_3:
|
|
|
+ if ((grp->owner == if_sync_serial_3) &&
|
|
|
+ interfaces[if_sync_serial_1].used) {
|
|
|
+ grp->owner = if_sync_serial_1;
|
|
|
+ } else
|
|
|
+ grp->used = 0;
|
|
|
+ break;
|
|
|
+ case if_scsi8_0:
|
|
|
+ if ((grp->owner == if_scsi8_0) &&
|
|
|
+ interfaces[if_scsi8_1].used) {
|
|
|
+ grp->owner = if_scsi8_1;
|
|
|
+ } else
|
|
|
+ grp->used = 0;
|
|
|
+ break;
|
|
|
+ case if_scsi8_1:
|
|
|
+ if ((grp->owner == if_scsi8_1) &&
|
|
|
+ interfaces[if_scsi8_0].used) {
|
|
|
+ grp->owner = if_scsi8_0;
|
|
|
+ } else
|
|
|
+ grp->used = 0;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ grp->used = 0;
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ grp->used = 0;
|
|
|
+ }
|
|
|
+ group_set = clear_group_from_set(group_set, grp);
|
|
|
+ }
|
|
|
+ interfaces[ioif].used = 0;
|
|
|
+ interfaces[ioif].owner = NULL;
|
|
|
+
|
|
|
+ DBG(printk("GPIO pins: available before: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
|
|
|
+ gpio_in_pins, gpio_out_pins, gpio_pb_pins));
|
|
|
+ DBG(printk("freeing pins: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
|
|
|
+ interfaces[ioif].gpio_g_in,
|
|
|
+ interfaces[ioif].gpio_g_out,
|
|
|
+ interfaces[ioif].gpio_b));
|
|
|
+
|
|
|
+ gpio_in_pins |= interfaces[ioif].gpio_g_in;
|
|
|
+ gpio_out_pins |= interfaces[ioif].gpio_g_out;
|
|
|
+ gpio_pb_pins |= interfaces[ioif].gpio_b;
|
|
|
+
|
|
|
+ DBG(printk("GPIO pins: available after: g_in=0x%08x g_out=0x%08x pb=0x%02x\n",
|
|
|
+ gpio_in_pins, gpio_out_pins, gpio_pb_pins));
|
|
|
+
|
|
|
+ local_irq_restore(flags);
|
|
|
+
|
|
|
+ notify_watchers();
|
|
|
+}
|
|
|
+
|
|
|
+/* Create a bitmask from bit 0 (inclusive) to bit stop_bit
|
|
|
+ (non-inclusive). stop_bit == 0 returns 0x0 */
|
|
|
+static inline unsigned int create_mask(const unsigned stop_bit)
|
|
|
+{
|
|
|
+ /* Avoid overflow */
|
|
|
+ if (stop_bit >= 32) {
|
|
|
+ return 0xffffffff;
|
|
|
+ }
|
|
|
+ return (1<<stop_bit)-1;
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+/* port can be 'a', 'b' or 'g' */
|
|
|
+int cris_io_interface_allocate_pins(const enum cris_io_interface ioif,
|
|
|
+ const char port,
|
|
|
+ const unsigned start_bit,
|
|
|
+ const unsigned stop_bit)
|
|
|
+{
|
|
|
+ unsigned int i;
|
|
|
+ unsigned int mask = 0;
|
|
|
+ unsigned int tmp_mask;
|
|
|
+ unsigned long int flags;
|
|
|
+ enum cris_io_interface *owners;
|
|
|
+
|
|
|
+ (void)cris_io_interface_init();
|
|
|
+
|
|
|
+ DBG(printk("cris_io_interface_allocate_pins: if=%d port=%c start=%u stop=%u\n",
|
|
|
+ ioif, port, start_bit, stop_bit));
|
|
|
+
|
|
|
+ if (!((start_bit <= stop_bit) &&
|
|
|
+ ((((port == 'a') || (port == 'b')) && (stop_bit < 8)) ||
|
|
|
+ ((port == 'g') && (stop_bit < 32))))) {
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ mask = create_mask(stop_bit + 1);
|
|
|
+ tmp_mask = create_mask(start_bit);
|
|
|
+ mask &= ~tmp_mask;
|
|
|
+
|
|
|
+ DBG(printk("cris_io_interface_allocate_pins: port=%c start=%u stop=%u mask=0x%08x\n",
|
|
|
+ port, start_bit, stop_bit, mask));
|
|
|
+
|
|
|
+ local_irq_save(flags);
|
|
|
+
|
|
|
+ switch (port) {
|
|
|
+ case 'a':
|
|
|
+ if ((gpio_pa_pins & mask) != mask) {
|
|
|
+ local_irq_restore(flags);
|
|
|
+ return -EBUSY;
|
|
|
+ }
|
|
|
+ owners = gpio_pa_owners;
|
|
|
+ gpio_pa_pins &= ~mask;
|
|
|
+ break;
|
|
|
+ case 'b':
|
|
|
+ if ((gpio_pb_pins & mask) != mask) {
|
|
|
+ local_irq_restore(flags);
|
|
|
+ return -EBUSY;
|
|
|
+ }
|
|
|
+ owners = gpio_pb_owners;
|
|
|
+ gpio_pb_pins &= ~mask;
|
|
|
+ break;
|
|
|
+ case 'g':
|
|
|
+ if (((gpio_in_pins & mask) != mask) ||
|
|
|
+ ((gpio_out_pins & mask) != mask)) {
|
|
|
+ local_irq_restore(flags);
|
|
|
+ return -EBUSY;
|
|
|
+ }
|
|
|
+ owners = gpio_pg_owners;
|
|
|
+ gpio_in_pins &= ~mask;
|
|
|
+ gpio_out_pins &= ~mask;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ local_irq_restore(flags);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ for (i = start_bit; i <= stop_bit; i++) {
|
|
|
+ owners[i] = ioif;
|
|
|
+ }
|
|
|
+ local_irq_restore(flags);
|
|
|
+
|
|
|
+ notify_watchers();
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+/* port can be 'a', 'b' or 'g' */
|
|
|
+int cris_io_interface_free_pins(const enum cris_io_interface ioif,
|
|
|
+ const char port,
|
|
|
+ const unsigned start_bit,
|
|
|
+ const unsigned stop_bit)
|
|
|
+{
|
|
|
+ unsigned int i;
|
|
|
+ unsigned int mask = 0;
|
|
|
+ unsigned int tmp_mask;
|
|
|
+ unsigned long int flags;
|
|
|
+ enum cris_io_interface *owners;
|
|
|
+
|
|
|
+ (void)cris_io_interface_init();
|
|
|
+
|
|
|
+ if (!((start_bit <= stop_bit) &&
|
|
|
+ ((((port == 'a') || (port == 'b')) && (stop_bit < 8)) ||
|
|
|
+ ((port == 'g') && (stop_bit < 32))))) {
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ mask = create_mask(stop_bit + 1);
|
|
|
+ tmp_mask = create_mask(start_bit);
|
|
|
+ mask &= ~tmp_mask;
|
|
|
+
|
|
|
+ DBG(printk("cris_io_interface_free_pins: port=%c start=%u stop=%u mask=0x%08x\n",
|
|
|
+ port, start_bit, stop_bit, mask));
|
|
|
+
|
|
|
+ local_irq_save(flags);
|
|
|
+
|
|
|
+ switch (port) {
|
|
|
+ case 'a':
|
|
|
+ if ((~gpio_pa_pins & mask) != mask) {
|
|
|
+ local_irq_restore(flags);
|
|
|
+ printk(KERN_CRIT "cris_io_interface_free_pins: Freeing free pins");
|
|
|
+ }
|
|
|
+ owners = gpio_pa_owners;
|
|
|
+ break;
|
|
|
+ case 'b':
|
|
|
+ if ((~gpio_pb_pins & mask) != mask) {
|
|
|
+ local_irq_restore(flags);
|
|
|
+ printk(KERN_CRIT "cris_io_interface_free_pins: Freeing free pins");
|
|
|
+ }
|
|
|
+ owners = gpio_pb_owners;
|
|
|
+ break;
|
|
|
+ case 'g':
|
|
|
+ if (((~gpio_in_pins & mask) != mask) ||
|
|
|
+ ((~gpio_out_pins & mask) != mask)) {
|
|
|
+ local_irq_restore(flags);
|
|
|
+ printk(KERN_CRIT "cris_io_interface_free_pins: Freeing free pins");
|
|
|
+ }
|
|
|
+ owners = gpio_pg_owners;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ owners = NULL; /* Cannot happen. Shut up, gcc! */
|
|
|
+ }
|
|
|
+
|
|
|
+ for (i = start_bit; i <= stop_bit; i++) {
|
|
|
+ if (owners[i] != ioif) {
|
|
|
+ printk(KERN_CRIT "cris_io_interface_free_pins: Freeing unowned pins");
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /* All was ok, change data. */
|
|
|
+ switch (port) {
|
|
|
+ case 'a':
|
|
|
+ gpio_pa_pins |= mask;
|
|
|
+ break;
|
|
|
+ case 'b':
|
|
|
+ gpio_pb_pins |= mask;
|
|
|
+ break;
|
|
|
+ case 'g':
|
|
|
+ gpio_in_pins |= mask;
|
|
|
+ gpio_out_pins |= mask;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ for (i = start_bit; i <= stop_bit; i++) {
|
|
|
+ owners[i] = if_unclaimed;
|
|
|
+ }
|
|
|
+ local_irq_restore(flags);
|
|
|
+ notify_watchers();
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+int cris_io_interface_register_watcher(void (*notify)(const unsigned int gpio_in_available,
|
|
|
+ const unsigned int gpio_out_available,
|
|
|
+ const unsigned char pa_available,
|
|
|
+ const unsigned char pb_available))
|
|
|
+{
|
|
|
+ struct watcher *w;
|
|
|
+
|
|
|
+ (void)cris_io_interface_init();
|
|
|
+
|
|
|
+ if (NULL == notify) {
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+ w = kmalloc(sizeof(*w), GFP_KERNEL);
|
|
|
+ if (!w) {
|
|
|
+ return -ENOMEM;
|
|
|
+ }
|
|
|
+ w->notify = notify;
|
|
|
+ w->next = watchers;
|
|
|
+ watchers = w;
|
|
|
+
|
|
|
+ w->notify((const unsigned int)gpio_in_pins,
|
|
|
+ (const unsigned int)gpio_out_pins,
|
|
|
+ (const unsigned char)gpio_pa_pins,
|
|
|
+ (const unsigned char)gpio_pb_pins);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+void cris_io_interface_delete_watcher(void (*notify)(const unsigned int gpio_in_available,
|
|
|
+ const unsigned int gpio_out_available,
|
|
|
+ const unsigned char pa_available,
|
|
|
+ const unsigned char pb_available))
|
|
|
+{
|
|
|
+ struct watcher *w = watchers, *prev = NULL;
|
|
|
+
|
|
|
+ (void)cris_io_interface_init();
|
|
|
+
|
|
|
+ while ((NULL != w) && (w->notify != notify)){
|
|
|
+ prev = w;
|
|
|
+ w = w->next;
|
|
|
+ }
|
|
|
+ if (NULL != w) {
|
|
|
+ if (NULL != prev) {
|
|
|
+ prev->next = w->next;
|
|
|
+ } else {
|
|
|
+ watchers = w->next;
|
|
|
+ }
|
|
|
+ kfree(w);
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ printk(KERN_WARNING "cris_io_interface_delete_watcher: Deleting unknown watcher 0x%p\n", notify);
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+static int cris_io_interface_init(void)
|
|
|
+{
|
|
|
+ static int first = 1;
|
|
|
+ int i;
|
|
|
+
|
|
|
+ if (!first) {
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+ first = 0;
|
|
|
+
|
|
|
+ for (i = 0; i<8; i++) {
|
|
|
+ gpio_pa_owners[i] = if_unclaimed;
|
|
|
+ gpio_pb_owners[i] = if_unclaimed;
|
|
|
+ gpio_pg_owners[i] = if_unclaimed;
|
|
|
+ }
|
|
|
+ for (; i<32; i++) {
|
|
|
+ gpio_pg_owners[i] = if_unclaimed;
|
|
|
+ }
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+module_init(cris_io_interface_init);
|
|
|
+
|
|
|
+
|
|
|
+EXPORT_SYMBOL(cris_request_io_interface);
|
|
|
+EXPORT_SYMBOL(cris_free_io_interface);
|
|
|
+EXPORT_SYMBOL(cris_io_interface_allocate_pins);
|
|
|
+EXPORT_SYMBOL(cris_io_interface_free_pins);
|
|
|
+EXPORT_SYMBOL(cris_io_interface_register_watcher);
|
|
|
+EXPORT_SYMBOL(cris_io_interface_delete_watcher);
|
Mikael Starvik