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@@ -72,19 +72,15 @@ ENDPROC(cpu_suspend_abort)
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/*
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/*
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* r0 = control register value
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* r0 = control register value
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*/
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*/
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+ .align 5
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ENTRY(cpu_resume_mmu)
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ENTRY(cpu_resume_mmu)
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ldr r3, =cpu_resume_after_mmu
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ldr r3, =cpu_resume_after_mmu
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- b cpu_resume_turn_mmu_on
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-ENDPROC(cpu_resume_mmu)
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- .ltorg
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- .align 5
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-ENTRY(cpu_resume_turn_mmu_on)
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mcr p15, 0, r0, c1, c0, 0 @ turn on MMU, I-cache, etc
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mcr p15, 0, r0, c1, c0, 0 @ turn on MMU, I-cache, etc
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mrc p15, 0, r0, c0, c0, 0 @ read id reg
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mrc p15, 0, r0, c0, c0, 0 @ read id reg
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mov r0, r0
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mov r0, r0
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mov r0, r0
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mov r0, r0
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mov pc, r3 @ jump to virtual address
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mov pc, r3 @ jump to virtual address
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-ENDPROC(cpu_resume_turn_mmu_on)
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+ENDPROC(cpu_resume_mmu)
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cpu_resume_after_mmu:
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cpu_resume_after_mmu:
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bl cpu_init @ restore the und/abt/irq banked regs
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bl cpu_init @ restore the und/abt/irq banked regs
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mov r0, #0 @ return zero on success
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mov r0, #0 @ return zero on success
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