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@@ -68,8 +68,8 @@
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#define DRV_MODULE_NAME "tg3"
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#define PFX DRV_MODULE_NAME ": "
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-#define DRV_MODULE_VERSION "3.68"
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-#define DRV_MODULE_RELDATE "November 02, 2006"
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+#define DRV_MODULE_VERSION "3.69"
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+#define DRV_MODULE_RELDATE "November 15, 2006"
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#define TG3_DEF_MAC_MODE 0
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#define TG3_DEF_RX_MODE 0
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@@ -4728,10 +4728,11 @@ static int tg3_poll_fw(struct tg3 *tp)
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u32 val;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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- for (i = 0; i < 400; i++) {
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+ /* Wait up to 20ms for init done. */
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+ for (i = 0; i < 200; i++) {
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if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
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return 0;
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- udelay(10);
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+ udelay(100);
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}
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return -ENODEV;
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}
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@@ -10365,7 +10366,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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u32 pci_state_reg, grc_misc_cfg;
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u32 val;
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u16 pci_cmd;
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- int err;
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+ int err, pcie_cap;
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/* Force memory write invalidate off. If we leave it on,
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* then on 5700_BX chips we have to enable a workaround.
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@@ -10540,8 +10541,19 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
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tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
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- if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
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+ pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
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+ if (pcie_cap != 0) {
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tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
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+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
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+ u16 lnkctl;
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+
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+ pci_read_config_word(tp->pdev,
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+ pcie_cap + PCI_EXP_LNKCTL,
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+ &lnkctl);
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+ if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
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+ tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
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+ }
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+ }
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/* If we have an AMD 762 or VIA K8T800 chipset, write
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* reordering to the mailbox registers done by the host
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@@ -11808,6 +11820,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
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else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
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tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
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+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
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(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
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tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
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} else {
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