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@@ -1,6 +1,107 @@
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-#ifndef __PLAT_OMAP_SRAM_H__
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-#define __PLAT_OMAP_SRAM_H__
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+/*
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+ * arch/arm/plat-omap/include/mach/sram.h
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+ *
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+ * Interface for functions that need to be run in internal SRAM
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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-extern int __init omap_sram_init(void);
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+#ifndef __ARCH_ARM_OMAP_SRAM_H
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+#define __ARCH_ARM_OMAP_SRAM_H
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-#endif /* __PLAT_OMAP_SRAM_H__ */
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+#ifndef __ASSEMBLY__
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+#include <asm/fncpy.h>
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+
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+int __init omap_sram_init(void);
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+
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+extern void *omap_sram_push_address(unsigned long size);
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+
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+/* Macro to push a function to the internal SRAM, using the fncpy API */
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+#define omap_sram_push(funcp, size) ({ \
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+ typeof(&(funcp)) _res = NULL; \
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+ void *_sram_address = omap_sram_push_address(size); \
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+ if (_sram_address) \
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+ _res = fncpy(_sram_address, &(funcp), size); \
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+ _res; \
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+})
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+
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+extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
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+
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+extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
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+ u32 base_cs, u32 force_unlock);
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+extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
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+ u32 mem_type);
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+extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
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+
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+extern u32 omap3_configure_core_dpll(
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+ u32 m2, u32 unlock_dll, u32 f, u32 inc,
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+ u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
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+ u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
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+ u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
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+ u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
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+extern void omap3_sram_restore_context(void);
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+
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+/* Do not use these */
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+extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
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+extern unsigned long omap1_sram_reprogram_clock_sz;
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+
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+extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
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+extern unsigned long omap24xx_sram_reprogram_clock_sz;
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+
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+extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
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+ u32 base_cs, u32 force_unlock);
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+extern unsigned long omap242x_sram_ddr_init_sz;
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+
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+extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
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+ int bypass);
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+extern unsigned long omap242x_sram_set_prcm_sz;
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+
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+extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
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+ u32 mem_type);
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+extern unsigned long omap242x_sram_reprogram_sdrc_sz;
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+
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+
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+extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
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+ u32 base_cs, u32 force_unlock);
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+extern unsigned long omap243x_sram_ddr_init_sz;
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+
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+extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
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+ int bypass);
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+extern unsigned long omap243x_sram_set_prcm_sz;
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+
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+extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
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+ u32 mem_type);
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+extern unsigned long omap243x_sram_reprogram_sdrc_sz;
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+
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+extern u32 omap3_sram_configure_core_dpll(
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+ u32 m2, u32 unlock_dll, u32 f, u32 inc,
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+ u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
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+ u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
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+ u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
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+ u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
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+extern unsigned long omap3_sram_configure_core_dpll_sz;
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+
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+#ifdef CONFIG_PM
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+extern void omap_push_sram_idle(void);
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+#else
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+static inline void omap_push_sram_idle(void) {}
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+#endif /* CONFIG_PM */
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+
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+#endif /* __ASSEMBLY__ */
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+
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+/*
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+ * OMAP2+: define the SRAM PA addresses.
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+ * Used by the SRAM management code and the idle sleep code.
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+ */
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+#define OMAP2_SRAM_PA 0x40200000
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+#define OMAP3_SRAM_PA 0x40200000
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+#ifdef CONFIG_OMAP4_ERRATA_I688
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+#define OMAP4_SRAM_PA 0x40304000
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+#define OMAP4_SRAM_VA 0xfe404000
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+#else
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+#define OMAP4_SRAM_PA 0x40300000
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+#endif
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+#define AM33XX_SRAM_PA 0x40300000
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+#endif
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