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@@ -291,3 +291,281 @@ int __init get_memcfg_numaq(void)
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smp_dump_qct();
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return 1;
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}
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+
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+/*
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+ * APIC driver for the IBM NUMAQ chipset.
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+ */
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+#define APIC_DEFINITION 1
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+#include <linux/threads.h>
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+#include <linux/cpumask.h>
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+#include <asm/mpspec.h>
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+#include <asm/genapic.h>
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+#include <asm/fixmap.h>
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+#include <asm/apicdef.h>
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+#include <linux/kernel.h>
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+#include <linux/string.h>
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+#include <linux/init.h>
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+#include <linux/numa.h>
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+#include <linux/smp.h>
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+#include <asm/numaq.h>
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+#include <asm/io.h>
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+#include <linux/mmzone.h>
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+#include <linux/nodemask.h>
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+
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+#define NUMAQ_APIC_DFR_VALUE (APIC_DFR_CLUSTER)
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+
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+static inline unsigned int numaq_get_apic_id(unsigned long x)
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+{
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+ return (x >> 24) & 0x0F;
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+}
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+
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+void default_send_IPI_mask_sequence(const struct cpumask *mask, int vector);
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+void default_send_IPI_mask_allbutself(const struct cpumask *mask, int vector);
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+
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+static inline void numaq_send_IPI_mask(const struct cpumask *mask, int vector)
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+{
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+ default_send_IPI_mask_sequence(mask, vector);
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+}
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+
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+static inline void numaq_send_IPI_allbutself(int vector)
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+{
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+ default_send_IPI_mask_allbutself(cpu_online_mask, vector);
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+}
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+
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+static inline void numaq_send_IPI_all(int vector)
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+{
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+ numaq_send_IPI_mask(cpu_online_mask, vector);
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+}
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+
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+extern void numaq_mps_oem_check(struct mpc_table *, char *, char *);
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+
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+#define NUMAQ_TRAMPOLINE_PHYS_LOW (0x8)
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+#define NUMAQ_TRAMPOLINE_PHYS_HIGH (0xa)
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+
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+/*
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+ * Because we use NMIs rather than the INIT-STARTUP sequence to
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+ * bootstrap the CPUs, the APIC may be in a weird state. Kick it:
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+ */
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+static inline void numaq_smp_callin_clear_local_apic(void)
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+{
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+ clear_local_APIC();
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+}
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+
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+static inline void
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+numaq_store_NMI_vector(unsigned short *high, unsigned short *low)
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+{
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+ printk("Storing NMI vector\n");
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+ *high =
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+ *((volatile unsigned short *)phys_to_virt(NUMAQ_TRAMPOLINE_PHYS_HIGH));
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+ *low =
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+ *((volatile unsigned short *)phys_to_virt(NUMAQ_TRAMPOLINE_PHYS_LOW));
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+}
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+
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+static inline const cpumask_t *numaq_target_cpus(void)
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+{
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+ return &CPU_MASK_ALL;
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+}
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+
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+static inline unsigned long
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+numaq_check_apicid_used(physid_mask_t bitmap, int apicid)
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+{
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+ return physid_isset(apicid, bitmap);
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+}
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+
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+static inline unsigned long numaq_check_apicid_present(int bit)
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+{
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+ return physid_isset(bit, phys_cpu_present_map);
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+}
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+
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+#define apicid_cluster(apicid) (apicid & 0xF0)
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+
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+static inline int numaq_apic_id_registered(void)
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+{
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+ return 1;
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+}
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+
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+static inline void numaq_init_apic_ldr(void)
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+{
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+ /* Already done in NUMA-Q firmware */
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+}
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+
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+static inline void numaq_setup_apic_routing(void)
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+{
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+ printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
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+ "NUMA-Q", nr_ioapics);
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+}
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+
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+/*
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+ * Skip adding the timer int on secondary nodes, which causes
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+ * a small but painful rift in the time-space continuum.
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+ */
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+static inline int numaq_multi_timer_check(int apic, int irq)
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+{
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+ return apic != 0 && irq == 0;
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+}
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+
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+static inline physid_mask_t numaq_ioapic_phys_id_map(physid_mask_t phys_map)
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+{
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+ /* We don't have a good way to do this yet - hack */
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+ return physids_promote(0xFUL);
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+}
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+
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+/* Mapping from cpu number to logical apicid */
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+extern u8 cpu_2_logical_apicid[];
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+
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+static inline int numaq_cpu_to_logical_apicid(int cpu)
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+{
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+ if (cpu >= nr_cpu_ids)
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+ return BAD_APICID;
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+ return (int)cpu_2_logical_apicid[cpu];
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+}
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+
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+/*
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+ * Supporting over 60 cpus on NUMA-Q requires a locality-dependent
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+ * cpu to APIC ID relation to properly interact with the intelligent
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+ * mode of the cluster controller.
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+ */
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+static inline int numaq_cpu_present_to_apicid(int mps_cpu)
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+{
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+ if (mps_cpu < 60)
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+ return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3));
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+ else
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+ return BAD_APICID;
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+}
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+
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+static inline int numaq_apicid_to_node(int logical_apicid)
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+{
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+ return logical_apicid >> 4;
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+}
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+
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+static inline physid_mask_t numaq_apicid_to_cpu_present(int logical_apicid)
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+{
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+ int node = numaq_apicid_to_node(logical_apicid);
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+ int cpu = __ffs(logical_apicid & 0xf);
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+
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+ return physid_mask_of_physid(cpu + 4*node);
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+}
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+
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+extern void *xquad_portio;
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+
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+static inline int numaq_check_phys_apicid_present(int boot_cpu_physical_apicid)
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+{
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+ return 1;
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+}
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+
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+/*
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+ * We use physical apicids here, not logical, so just return the default
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+ * physical broadcast to stop people from breaking us
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+ */
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+static inline unsigned int numaq_cpu_mask_to_apicid(const cpumask_t *cpumask)
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+{
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+ return 0x0F;
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+}
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+
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+static inline unsigned int
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+numaq_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
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+ const struct cpumask *andmask)
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+{
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+ return 0x0F;
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+}
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+
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+/* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */
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+static inline int numaq_phys_pkg_id(int cpuid_apic, int index_msb)
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+{
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+ return cpuid_apic >> index_msb;
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+}
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+static int __numaq_mps_oem_check(struct mpc_table *mpc, char *oem, char *productid)
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+{
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+ numaq_mps_oem_check(mpc, oem, productid);
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+ return found_numaq;
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+}
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+
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+static int probe_numaq(void)
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+{
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+ /* already know from get_memcfg_numaq() */
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+ return found_numaq;
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+}
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+
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+static void numaq_vector_allocation_domain(int cpu, cpumask_t *retmask)
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+{
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+ /* Careful. Some cpus do not strictly honor the set of cpus
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+ * specified in the interrupt destination when using lowest
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+ * priority interrupt delivery mode.
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+ *
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+ * In particular there was a hyperthreading cpu observed to
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+ * deliver interrupts to the wrong hyperthread when only one
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+ * hyperthread was specified in the interrupt desitination.
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+ */
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+ *retmask = (cpumask_t){ { [0] = APIC_ALL_CPUS, } };
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+}
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+
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+static void numaq_setup_portio_remap(void)
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+{
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+ int num_quads = num_online_nodes();
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+
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+ if (num_quads <= 1)
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+ return;
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+
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+ printk("Remapping cross-quad port I/O for %d quads\n", num_quads);
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+ xquad_portio = ioremap(XQUAD_PORTIO_BASE, num_quads*XQUAD_PORTIO_QUAD);
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+ printk("xquad_portio vaddr 0x%08lx, len %08lx\n",
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+ (u_long) xquad_portio, (u_long) num_quads*XQUAD_PORTIO_QUAD);
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+}
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+
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+struct genapic apic_numaq = {
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+
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+ .name = "NUMAQ",
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+ .probe = probe_numaq,
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+ .acpi_madt_oem_check = NULL,
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+ .apic_id_registered = numaq_apic_id_registered,
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+
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+ .irq_delivery_mode = dest_LowestPrio,
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+ /* physical delivery on LOCAL quad: */
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+ .irq_dest_mode = 0,
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+
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+ .target_cpus = numaq_target_cpus,
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+ .disable_esr = 1,
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+ .dest_logical = APIC_DEST_LOGICAL,
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+ .check_apicid_used = numaq_check_apicid_used,
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+ .check_apicid_present = numaq_check_apicid_present,
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+
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+ .vector_allocation_domain = numaq_vector_allocation_domain,
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+ .init_apic_ldr = numaq_init_apic_ldr,
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+
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+ .ioapic_phys_id_map = numaq_ioapic_phys_id_map,
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+ .setup_apic_routing = numaq_setup_apic_routing,
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+ .multi_timer_check = numaq_multi_timer_check,
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+ .apicid_to_node = numaq_apicid_to_node,
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+ .cpu_to_logical_apicid = numaq_cpu_to_logical_apicid,
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+ .cpu_present_to_apicid = numaq_cpu_present_to_apicid,
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+ .apicid_to_cpu_present = numaq_apicid_to_cpu_present,
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+ .setup_portio_remap = numaq_setup_portio_remap,
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+ .check_phys_apicid_present = numaq_check_phys_apicid_present,
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+ .enable_apic_mode = NULL,
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+ .phys_pkg_id = numaq_phys_pkg_id,
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+ .mps_oem_check = __numaq_mps_oem_check,
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+
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+ .get_apic_id = numaq_get_apic_id,
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+ .set_apic_id = NULL,
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+ .apic_id_mask = 0x0F << 24,
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+
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+ .cpu_mask_to_apicid = numaq_cpu_mask_to_apicid,
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+ .cpu_mask_to_apicid_and = numaq_cpu_mask_to_apicid_and,
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+
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+ .send_IPI_mask = numaq_send_IPI_mask,
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+ .send_IPI_mask_allbutself = NULL,
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+ .send_IPI_allbutself = numaq_send_IPI_allbutself,
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+ .send_IPI_all = numaq_send_IPI_all,
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+ .send_IPI_self = NULL,
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+
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+ .wakeup_cpu = NULL,
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+ .trampoline_phys_low = NUMAQ_TRAMPOLINE_PHYS_LOW,
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+ .trampoline_phys_high = NUMAQ_TRAMPOLINE_PHYS_HIGH,
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+
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+ /* We don't do anything here because we use NMI's to boot instead */
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+ .wait_for_init_deassert = NULL,
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+
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+ .smp_callin_clear_local_apic = numaq_smp_callin_clear_local_apic,
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+ .store_NMI_vector = numaq_store_NMI_vector,
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+ .inquire_remote_apic = NULL,
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+};
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Ingo Molnar