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@@ -30,6 +30,7 @@
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#include <linux/delay.h>
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#include <linux/spi/spi.h>
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+#include <linux/dmaengine.h>
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#include <mach/dma.h>
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@@ -162,12 +163,23 @@ struct spi_tegra_data {
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* require transfers to be 4 byte aligned we need a bounce buffer
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* for the generic case.
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*/
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+ int dma_req_len;
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+#if defined(CONFIG_TEGRA_SYSTEM_DMA)
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struct tegra_dma_req rx_dma_req;
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struct tegra_dma_channel *rx_dma;
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+#else
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+ struct dma_chan *rx_dma;
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+ struct dma_slave_config sconfig;
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+ struct dma_async_tx_descriptor *rx_dma_desc;
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+ dma_cookie_t rx_cookie;
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+#endif
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u32 *rx_bb;
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dma_addr_t rx_bb_phys;
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};
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+#if !defined(CONFIG_TEGRA_SYSTEM_DMA)
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+static void tegra_spi_rx_dma_complete(void *args);
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+#endif
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static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi,
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unsigned long reg)
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@@ -190,10 +202,24 @@ static void spi_tegra_go(struct spi_tegra_data *tspi)
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val = spi_tegra_readl(tspi, SLINK_DMA_CTL);
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val &= ~SLINK_DMA_BLOCK_SIZE(~0) & ~SLINK_DMA_EN;
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- val |= SLINK_DMA_BLOCK_SIZE(tspi->rx_dma_req.size / 4 - 1);
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+ val |= SLINK_DMA_BLOCK_SIZE(tspi->dma_req_len / 4 - 1);
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spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
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-
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+#if defined(CONFIG_TEGRA_SYSTEM_DMA)
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+ tspi->rx_dma_req.size = tspi->dma_req_len;
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tegra_dma_enqueue_req(tspi->rx_dma, &tspi->rx_dma_req);
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+#else
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+ tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma,
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+ tspi->rx_bb_phys, tspi->dma_req_len,
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+ DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
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+ if (!tspi->rx_dma_desc) {
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+ dev_err(&tspi->pdev->dev, "dmaengine slave prep failed\n");
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+ return;
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+ }
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+ tspi->rx_dma_desc->callback = tegra_spi_rx_dma_complete;
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+ tspi->rx_dma_desc->callback_param = tspi;
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+ tspi->rx_cookie = dmaengine_submit(tspi->rx_dma_desc);
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+ dma_async_issue_pending(tspi->rx_dma);
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+#endif
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val |= SLINK_DMA_EN;
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spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
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@@ -221,7 +247,7 @@ static unsigned spi_tegra_fill_tx_fifo(struct spi_tegra_data *tspi,
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spi_tegra_writel(tspi, val, SLINK_TX_FIFO);
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}
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- tspi->rx_dma_req.size = len / tspi->cur_bytes_per_word * 4;
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+ tspi->dma_req_len = len / tspi->cur_bytes_per_word * 4;
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return len;
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}
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@@ -318,9 +344,8 @@ static void spi_tegra_start_message(struct spi_device *spi,
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spi_tegra_start_transfer(spi, t);
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}
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-static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
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+static void handle_spi_rx_dma_complete(struct spi_tegra_data *tspi)
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{
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- struct spi_tegra_data *tspi = req->dev;
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unsigned long flags;
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struct spi_message *m;
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struct spi_device *spi;
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@@ -380,6 +405,19 @@ static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
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spin_unlock_irqrestore(&tspi->lock, flags);
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}
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+#if defined(CONFIG_TEGRA_SYSTEM_DMA)
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+static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
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+{
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+ struct spi_tegra_data *tspi = req->dev;
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+ handle_spi_rx_dma_complete(tspi);
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+}
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+#else
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+static void tegra_spi_rx_dma_complete(void *args)
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+{
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+ struct spi_tegra_data *tspi = args;
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+ handle_spi_rx_dma_complete(tspi);
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+}
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+#endif
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static int spi_tegra_setup(struct spi_device *spi)
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{
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@@ -471,6 +509,9 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
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struct spi_tegra_data *tspi;
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struct resource *r;
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int ret;
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+#if !defined(CONFIG_TEGRA_SYSTEM_DMA)
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+ dma_cap_mask_t mask;
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+#endif
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master = spi_alloc_master(&pdev->dev, sizeof *tspi);
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if (master == NULL) {
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@@ -522,12 +563,24 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
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INIT_LIST_HEAD(&tspi->queue);
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+#if defined(CONFIG_TEGRA_SYSTEM_DMA)
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tspi->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
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if (!tspi->rx_dma) {
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dev_err(&pdev->dev, "can not allocate rx dma channel\n");
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ret = -ENODEV;
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goto err3;
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}
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+#else
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+ dma_cap_zero(mask);
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+ dma_cap_set(DMA_SLAVE, mask);
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+ tspi->rx_dma = dma_request_channel(mask, NULL, NULL);
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+ if (!tspi->rx_dma) {
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+ dev_err(&pdev->dev, "can not allocate rx dma channel\n");
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+ ret = -ENODEV;
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+ goto err3;
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+ }
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+
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+#endif
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tspi->rx_bb = dma_alloc_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
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&tspi->rx_bb_phys, GFP_KERNEL);
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@@ -537,6 +590,7 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
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goto err4;
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}
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+#if defined(CONFIG_TEGRA_SYSTEM_DMA)
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tspi->rx_dma_req.complete = tegra_spi_rx_dma_complete;
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tspi->rx_dma_req.to_memory = 1;
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tspi->rx_dma_req.dest_addr = tspi->rx_bb_phys;
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@@ -546,6 +600,23 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
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tspi->rx_dma_req.source_wrap = 4;
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tspi->rx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
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tspi->rx_dma_req.dev = tspi;
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+#else
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+ /* Dmaengine Dma slave config */
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+ tspi->sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
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+ tspi->sconfig.dst_addr = tspi->phys + SLINK_RX_FIFO;
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+ tspi->sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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+ tspi->sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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+ tspi->sconfig.slave_id = spi_tegra_req_sels[pdev->id];
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+ tspi->sconfig.src_maxburst = 1;
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+ tspi->sconfig.dst_maxburst = 1;
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+ ret = dmaengine_device_control(tspi->rx_dma,
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+ DMA_SLAVE_CONFIG, (unsigned long) &tspi->sconfig);
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+ if (ret < 0) {
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+ dev_err(&pdev->dev, "can not do slave configure for dma %d\n",
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+ ret);
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+ goto err4;
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+ }
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+#endif
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master->dev.of_node = pdev->dev.of_node;
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ret = spi_register_master(master);
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@@ -559,7 +630,11 @@ err5:
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dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
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tspi->rx_bb, tspi->rx_bb_phys);
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err4:
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+#if defined(CONFIG_TEGRA_SYSTEM_DMA)
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tegra_dma_free_channel(tspi->rx_dma);
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+#else
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+ dma_release_channel(tspi->rx_dma);
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+#endif
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err3:
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clk_put(tspi->clk);
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err2:
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@@ -581,7 +656,11 @@ static int __devexit spi_tegra_remove(struct platform_device *pdev)
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tspi = spi_master_get_devdata(master);
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spi_unregister_master(master);
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+#if defined(CONFIG_TEGRA_SYSTEM_DMA)
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tegra_dma_free_channel(tspi->rx_dma);
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+#else
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+ dma_release_channel(tspi->rx_dma);
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+#endif
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dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
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tspi->rx_bb, tspi->rx_bb_phys);
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