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@@ -184,23 +184,37 @@ __v7_setup:
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stmia r12, {r0-r5, r7, r9, r11, lr}
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stmia r12, {r0-r5, r7, r9, r11, lr}
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bl v7_flush_dcache_all
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bl v7_flush_dcache_all
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ldmia r12, {r0-r5, r7, r9, r11, lr}
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ldmia r12, {r0-r5, r7, r9, r11, lr}
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+
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+ mrc p15, 0, r0, c0, c0, 0 @ read main ID register
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+ and r10, r0, #0xff000000 @ ARM?
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+ teq r10, #0x41000000
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+ bne 2f
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+ and r5, r0, #0x00f00000 @ variant
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+ and r6, r0, #0x0000000f @ revision
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+ orr r0, r6, r5, lsr #20-4 @ combine variant and revision
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+
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#ifdef CONFIG_ARM_ERRATA_430973
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#ifdef CONFIG_ARM_ERRATA_430973
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- mrc p15, 0, r10, c1, c0, 1 @ read aux control register
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- orr r10, r10, #(1 << 6) @ set IBE to 1
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- mcr p15, 0, r10, c1, c0, 1 @ write aux control register
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+ teq r5, #0x00100000 @ only present in r1p*
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+ mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
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+ orreq r10, r10, #(1 << 6) @ set IBE to 1
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+ mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
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#endif
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#endif
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#ifdef CONFIG_ARM_ERRATA_458693
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#ifdef CONFIG_ARM_ERRATA_458693
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- mrc p15, 0, r10, c1, c0, 1 @ read aux control register
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- orr r10, r10, #(1 << 5) @ set L1NEON to 1
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- orr r10, r10, #(1 << 9) @ set PLDNOP to 1
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- mcr p15, 0, r10, c1, c0, 1 @ write aux control register
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+ teq r0, #0x20 @ only present in r2p0
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+ mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
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+ orreq r10, r10, #(1 << 5) @ set L1NEON to 1
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+ orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
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+ mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
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#endif
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#endif
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#ifdef CONFIG_ARM_ERRATA_460075
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#ifdef CONFIG_ARM_ERRATA_460075
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- mrc p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
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- orr r10, r10, #(1 << 22) @ set the Write Allocate disable bit
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- mcr p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
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+ teq r0, #0x20 @ only present in r2p0
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+ mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
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+ tsteq r10, #1 << 22
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+ orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
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+ mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
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#endif
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#endif
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- mov r10, #0
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+
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+2: mov r10, #0
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#ifdef HARVARD_CACHE
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#ifdef HARVARD_CACHE
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mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
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mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
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#endif
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#endif
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