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@@ -109,12 +109,6 @@ phy_SwChnlStepByStep(
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);
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static RT_STATUS
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phy_ConfigBBWithPgHeaderFile(struct net_device* dev,u8 ConfigType);
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-#ifdef RTL8192SE
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-static u32 phy_FwRFSerialRead( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset);
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-static u32 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset);
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-static void phy_FwRFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
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-static void phy_RFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data);
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-#endif
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static long phy_TxPwrIdxToDbm( struct net_device* dev, WIRELESS_MODE WirelessMode, u8 TxPwrIdx);
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static u8 phy_DbmToTxPwrIdx( struct net_device* dev, WIRELESS_MODE WirelessMode, long PowerInDbm);
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void phy_SetFwCmdIOCallback(struct net_device* dev);
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@@ -705,406 +699,6 @@ void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32
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}
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-#ifdef RTL8192SE
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-/*-----------------------------------------------------------------------------
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- * Function: phy_FwRFSerialRead()
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- *
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- * Overview: We support firmware to execute RF-R/W.
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- *
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- * Input: NONE
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- *
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- * Output: NONE
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- *
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- * Return: NONE
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- *
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- * Revised History:
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- * When Who Remark
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- * 01/21/2008 MHC Create Version 0.
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- *
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- *---------------------------------------------------------------------------*/
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-//use in phy only
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-static u32
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-phy_FwRFSerialRead(
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- struct net_device* dev,
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- RF90_RADIO_PATH_E eRFPath,
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- u32 Offset )
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-{
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- u32 retValue = 0;
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- //u32 Data = 0;
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- //u8 time = 0;
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-#if 0
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- //DbgPrint("FW RF CTRL\n\r");
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- /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
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- not execute the scheme in the initial step. Otherwise, RF-R/W will waste
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- much time. This is only for site survey. */
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- // 1. Read operation need not insert data. bit 0-11
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- //Data &= bMask12Bits;
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- // 2. Write RF register address. Bit 12-19
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- Data |= ((Offset&0xFF)<<12);
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- // 3. Write RF path. bit 20-21
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- Data |= ((eRFPath&0x3)<<20);
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- // 4. Set RF read indicator. bit 22=0
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- //Data |= 0x00000;
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- // 5. Trigger Fw to operate the command. bit 31
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- Data |= 0x80000000;
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- // 6. We can not execute read operation if bit 31 is 1.
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- while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
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- {
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- // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
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- if (time++ < 100)
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- {
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- //DbgPrint("FW not finish RF-R Time=%d\n\r", time);
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- delay_us(10);
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- }
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- else
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- break;
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- }
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- // 7. Execute read operation.
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- PlatformIOWrite4Byte(dev, QPNR, Data);
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- // 8. Check if firmawre send back RF content.
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- while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
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- {
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- // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
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- if (time++ < 100)
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- {
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- //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
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- delay_us(10);
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- }
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- else
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- return (0);
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- }
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- retValue = PlatformIORead4Byte(dev, RF_DATA);
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-#endif
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- return (retValue);
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-
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-} /* phy_FwRFSerialRead */
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-
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-/*-----------------------------------------------------------------------------
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- * Function: phy_FwRFSerialWrite()
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- *
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- * Overview: We support firmware to execute RF-R/W.
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- *
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- * Input: NONE
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- *
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- * Output: NONE
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- *
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- * Return: NONE
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- *
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- * Revised History:
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- * When Who Remark
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- * 01/21/2008 MHC Create Version 0.
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- *
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- *---------------------------------------------------------------------------*/
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-//use in phy only
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-static void
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-phy_FwRFSerialWrite(
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- struct net_device* dev,
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- RF90_RADIO_PATH_E eRFPath,
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- u32 Offset,
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- u32 Data )
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-{
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-#if 0
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- u8 time = 0;
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- DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
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- /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
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- not execute the scheme in the initial step. Otherwise, RF-R/W will waste
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- much time. This is only for site survey. */
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-
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- // 1. Set driver write bit and 12 bit data. bit 0-11
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- //Data &= bMask12Bits; // Done by uper layer.
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- // 2. Write RF register address. bit 12-19
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- Data |= ((Offset&0xFF)<<12);
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- // 3. Write RF path. bit 20-21
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- Data |= ((eRFPath&0x3)<<20);
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- // 4. Set RF write indicator. bit 22=1
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- Data |= 0x400000;
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- // 5. Trigger Fw to operate the command. bit 31=1
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- Data |= 0x80000000;
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-
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- // 6. Write operation. We can not write if bit 31 is 1.
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- while (PlatformIORead4Byte(dev, QPNR)&0x80000000)
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- {
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- // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
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- if (time++ < 100)
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- {
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- //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
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- delay_us(10);
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- }
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- else
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- break;
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- }
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- // 7. No matter check bit. We always force the write. Because FW will
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- // not accept the command.
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- PlatformIOWrite4Byte(dev, QPNR, Data);
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- /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
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- to finish RF write operation. */
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- /* 2008/01/17 MH We support delay in firmware side now. */
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- //delay_us(20);
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-#endif
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-} /* phy_FwRFSerialWrite */
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-
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-/**
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-* Function: phy_RFSerialRead
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-*
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-* OverView: Read regster from RF chips
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-*
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-* Input:
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-* PADAPTER Adapter,
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-* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
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-* u32 Offset, //The target address to be read
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-*
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-* Output: None
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-* Return: u32 reback value
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-* Note: Threre are three types of serial operations:
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-* 1. Software serial write
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-* 2. Hardware LSSI-Low Speed Serial Interface
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-* 3. Hardware HSSI-High speed
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-* serial write. Driver need to implement (1) and (2).
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-* This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
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-*/
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-//use in phy only
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-static u32 phy_RFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset)
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-{
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-
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- u32 retValue = 0;
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- struct r8192_priv *priv = ieee80211_priv(dev);
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- BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
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- u32 NewOffset;
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- u8 RfPiEnable=0;
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-
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-
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- //
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- // Make sure RF register offset is correct
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- //
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- Offset &= 0x3f;
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-
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- //
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- // Switch page for 8256 RF IC
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- //
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- if( priv->rf_chip == RF_8256 ||
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- priv->rf_chip == RF_8225 ||
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- priv->rf_chip == RF_6052)
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- {
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- //analog to digital off, for protection
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- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
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-
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- if(Offset>=31)
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- {
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- priv->RFReadPageCnt[2]++;//cosa add for debug
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- priv->RfReg0Value[eRFPath] |= 0x140;
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-
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- // Switch to Reg_Mode2 for Reg31~45
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- rtl8192_setBBreg(dev,
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- pPhyReg->rf3wireOffset,
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- bMaskDWord,
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- (priv->RfReg0Value[eRFPath] << 16) );
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-
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- // Modified Offset
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- NewOffset = Offset - 30;
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-
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- }else if(Offset>=16)
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- {
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- priv->RFReadPageCnt[1]++;//cosa add for debug
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- priv->RfReg0Value[eRFPath] |= 0x100;
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- priv->RfReg0Value[eRFPath] &= (~0x40);
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-
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- // Switch to Reg_Mode1 for Reg16~30
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- rtl8192_setBBreg(dev,
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- pPhyReg->rf3wireOffset,
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- bMaskDWord,
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- (priv->RfReg0Value[eRFPath] << 16) );
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-
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- // Modified Offset
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- NewOffset = Offset - 15;
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- }
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- else
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- {
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- priv->RFReadPageCnt[0]++;//cosa add for debug
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- NewOffset = Offset;
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- }
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- }
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- else
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- NewOffset = Offset;
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-
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- //
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- // Put desired read address to LSSI control register
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- //
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- rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
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-
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- //
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- // Issue a posedge trigger
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- //
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- rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
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- rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
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-
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- // TODO: we should not delay such a long time. Ask help from SD3
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- mdelay(1);
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-
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- retValue = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
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-
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- // Switch back to Reg_Mode0;
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- if( priv->rf_chip == RF_8256 ||
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- priv->rf_chip == RF_8225 ||
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- priv->rf_chip == RF_0222D)
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- {
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- if (Offset >= 0x10)
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- {
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- priv->RfReg0Value[eRFPath] &= 0xebf;
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-
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- rtl8192_setBBreg(
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- dev,
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- pPhyReg->rf3wireOffset,
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- bMaskDWord,
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- (priv->RfReg0Value[eRFPath] << 16) );
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- }
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-
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- //analog to digital on
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- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
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- }
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-
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- return retValue;
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-}
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-
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-
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-
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-/**
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-* Function: phy_RFSerialWrite
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-*
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-* OverView: Write data to RF register (page 8~)
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-*
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-* Input:
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-* PADAPTER Adapter,
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-* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
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-* u32 Offset, //The target address to be read
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-* u32 Data //The new register Data in the target bit position
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-* //of the target to be read
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-*
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-* Output: None
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-* Return: None
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-* Note: Threre are three types of serial operations:
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-* 1. Software serial write
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-* 2. Hardware LSSI-Low Speed Serial Interface
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-* 3. Hardware HSSI-High speed
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-* serial write. Driver need to implement (1) and (2).
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-* This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
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- *
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- * Note: For RF8256 only
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- * The total count of RTL8256(Zebra4) register is around 36 bit it only employs
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- * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
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- * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
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- * programming guide" for more details.
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- * Thus, we define a sub-finction for RTL8526 register address conversion
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- * ===========================================================
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- * Register Mode RegCTL[1] RegCTL[0] Note
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- * (Reg00[12]) (Reg00[10])
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- * ===========================================================
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- * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
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- * ------------------------------------------------------------------
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- * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
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- * ------------------------------------------------------------------
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- * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
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- * ------------------------------------------------------------------
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-*/
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-////use in phy only
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-static void
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-phy_RFSerialWrite(
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- struct net_device* dev,
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- RF90_RADIO_PATH_E eRFPath,
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- u32 Offset,
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- u32 Data
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- )
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-{
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- u32 DataAndAddr = 0;
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- struct r8192_priv *priv = ieee80211_priv(dev);
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- BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
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- u32 NewOffset;
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-
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- Offset &= 0x3f;
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-
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- // Shadow Update
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- PHY_RFShadowWrite(dev, eRFPath, Offset, Data);
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-
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-
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- // Switch page for 8256 RF IC
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- if( priv->rf_chip == RF_8256 ||
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- priv->rf_chip == RF_8225 ||
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- priv->rf_chip == RF_0222D)
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- {
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- //analog to digital off, for protection
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- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
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-
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- if(Offset>=31)
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- {
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- priv->RFWritePageCnt[2]++;//cosa add for debug
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- priv->RfReg0Value[eRFPath] |= 0x140;
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-
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- rtl8192_setBBreg(dev,
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- pPhyReg->rf3wireOffset,
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- bMaskDWord,
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- (priv->RfReg0Value[eRFPath] << 16) );
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-
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- NewOffset = Offset - 30;
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-
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- }else if(Offset>=16)
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- {
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- priv->RFWritePageCnt[1]++;//cosa add for debug
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- priv->RfReg0Value[eRFPath] |= 0x100;
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- priv->RfReg0Value[eRFPath] &= (~0x40);
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-
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-
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- rtl8192_setBBreg(dev,
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- pPhyReg->rf3wireOffset,
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- bMaskDWord,
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- (priv->RfReg0Value[eRFPath] << 16) );
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-
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- NewOffset = Offset - 15;
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- }
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- else
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- {
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- priv->RFWritePageCnt[0]++;//cosa add for debug
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- NewOffset = Offset;
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- }
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- }
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- else
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- NewOffset = Offset;
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-
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- //
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- // Put write addr in [5:0] and write data in [31:16]
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- //
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- DataAndAddr = (Data<<16) | (NewOffset&0x3f);
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-
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- //
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- // Write Operation
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- //
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- rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
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-
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-
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- if(Offset==0x0)
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- priv->RfReg0Value[eRFPath] = Data;
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-
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- // Switch back to Reg_Mode0;
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- if( priv->rf_chip == RF_8256 ||
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- priv->rf_chip == RF_8225 ||
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- priv->rf_chip == RF_0222D)
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- {
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- if (Offset >= 0x10)
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- {
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- if(Offset != 0)
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- {
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- priv->RfReg0Value[eRFPath] &= 0xebf;
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- rtl8192_setBBreg(
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- dev,
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- pPhyReg->rf3wireOffset,
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- bMaskDWord,
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- (priv->RfReg0Value[eRFPath] << 16) );
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- }
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- }
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- //analog to digital on
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- rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
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- }
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-
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-}
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-#else
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/**
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* Function: phy_RFSerialRead
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*
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@@ -1276,7 +870,6 @@ phy_RFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u3
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}
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#endif
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-#endif
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/**
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* Function: phy_CalculateBitShift
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@@ -3376,9 +2969,7 @@ void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EX
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#endif
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if((priv->up) )// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower) )
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{
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-#ifdef RTL8192SE
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- PHY_SetBWModeCallback8192S(dev);
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-#elif defined(RTL8192SU)
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+#if defined(RTL8192SU)
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SetBWModeCallback8192SUsbWorkItem(dev);
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#endif
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}
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@@ -3495,9 +3086,7 @@ u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
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if((priv->up))// && !(RT_CANNOT_IO(Adapter) && Adapter->bInSetPower))
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{
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-#ifdef RTL8192SE
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- PHY_SwChnlCallback8192S(dev);
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-#elif defined(RTL8192SU)
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+#if defined(RTL8192SU)
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SwChnlCallback8192SUsbWorkItem(dev);
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#endif
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#ifdef TO_DO_LIST
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@@ -3750,7 +3339,7 @@ phy_SwChnlStepByStep(
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case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!!
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for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
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{
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-#if (defined RTL8192SE ||defined RTL8192SU )
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+#if defined RTL8192SU
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// For new T65 RF 0222d register 0x18 bit 0-9 = channel number.
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rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f, (CurrentCmd->Para2));
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//printk("====>%x, %x, read_back:%x\n", CurrentCmd->Para2,CurrentCmd->Para1, rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, 0x1f));
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Bartlomiej Zolnierkiewicz