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@@ -44,9 +44,9 @@ struct cpu_hw_counters {
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};
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/*
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- * struct pmc_x86_ops - performance counter x86 ops
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+ * struct x86_pmu - generic x86 pmu
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*/
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-struct pmc_x86_ops {
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+struct x86_pmu {
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u64 (*save_disable_all)(void);
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void (*restore_all)(u64);
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u64 (*get_status)(u64);
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@@ -60,7 +60,7 @@ struct pmc_x86_ops {
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int max_events;
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};
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-static struct pmc_x86_ops *pmc_ops __read_mostly;
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+static struct x86_pmu *x86_pmu __read_mostly;
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static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = {
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.enabled = 1,
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@@ -82,12 +82,12 @@ static const u64 intel_perfmon_event_map[] =
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[PERF_COUNT_BUS_CYCLES] = 0x013c,
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};
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-static u64 pmc_intel_event_map(int event)
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+static u64 intel_pmu_event_map(int event)
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{
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return intel_perfmon_event_map[event];
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}
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-static u64 pmc_intel_raw_event(u64 event)
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+static u64 intel_pmu_raw_event(u64 event)
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{
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#define CORE_EVNTSEL_EVENT_MASK 0x000000FFULL
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#define CORE_EVNTSEL_UNIT_MASK 0x0000FF00ULL
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@@ -114,12 +114,12 @@ static const u64 amd_perfmon_event_map[] =
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[PERF_COUNT_BRANCH_MISSES] = 0x00c5,
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};
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-static u64 pmc_amd_event_map(int event)
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+static u64 amd_pmu_event_map(int event)
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{
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return amd_perfmon_event_map[event];
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}
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-static u64 pmc_amd_raw_event(u64 event)
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+static u64 amd_pmu_raw_event(u64 event)
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{
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#define K7_EVNTSEL_EVENT_MASK 0x7000000FFULL
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#define K7_EVNTSEL_UNIT_MASK 0x00000FF00ULL
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@@ -184,12 +184,12 @@ static bool reserve_pmc_hardware(void)
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disable_lapic_nmi_watchdog();
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for (i = 0; i < nr_counters_generic; i++) {
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- if (!reserve_perfctr_nmi(pmc_ops->perfctr + i))
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+ if (!reserve_perfctr_nmi(x86_pmu->perfctr + i))
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goto perfctr_fail;
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}
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for (i = 0; i < nr_counters_generic; i++) {
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- if (!reserve_evntsel_nmi(pmc_ops->eventsel + i))
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+ if (!reserve_evntsel_nmi(x86_pmu->eventsel + i))
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goto eventsel_fail;
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}
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@@ -197,13 +197,13 @@ static bool reserve_pmc_hardware(void)
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eventsel_fail:
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for (i--; i >= 0; i--)
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- release_evntsel_nmi(pmc_ops->eventsel + i);
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+ release_evntsel_nmi(x86_pmu->eventsel + i);
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i = nr_counters_generic;
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perfctr_fail:
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for (i--; i >= 0; i--)
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- release_perfctr_nmi(pmc_ops->perfctr + i);
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+ release_perfctr_nmi(x86_pmu->perfctr + i);
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if (nmi_watchdog == NMI_LOCAL_APIC)
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enable_lapic_nmi_watchdog();
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@@ -216,8 +216,8 @@ static void release_pmc_hardware(void)
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int i;
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for (i = 0; i < nr_counters_generic; i++) {
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- release_perfctr_nmi(pmc_ops->perfctr + i);
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- release_evntsel_nmi(pmc_ops->eventsel + i);
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+ release_perfctr_nmi(x86_pmu->perfctr + i);
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+ release_evntsel_nmi(x86_pmu->eventsel + i);
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}
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if (nmi_watchdog == NMI_LOCAL_APIC)
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@@ -293,14 +293,14 @@ static int __hw_perf_counter_init(struct perf_counter *counter)
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* Raw event type provide the config in the event structure
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*/
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if (perf_event_raw(hw_event)) {
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- hwc->config |= pmc_ops->raw_event(perf_event_config(hw_event));
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+ hwc->config |= x86_pmu->raw_event(perf_event_config(hw_event));
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} else {
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- if (perf_event_id(hw_event) >= pmc_ops->max_events)
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+ if (perf_event_id(hw_event) >= x86_pmu->max_events)
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return -EINVAL;
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/*
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* The generic map:
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*/
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- hwc->config |= pmc_ops->event_map(perf_event_id(hw_event));
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+ hwc->config |= x86_pmu->event_map(perf_event_id(hw_event));
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}
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counter->destroy = hw_perf_counter_destroy;
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@@ -308,7 +308,7 @@ static int __hw_perf_counter_init(struct perf_counter *counter)
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return 0;
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}
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-static u64 pmc_intel_save_disable_all(void)
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+static u64 intel_pmu_save_disable_all(void)
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{
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u64 ctrl;
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@@ -318,7 +318,7 @@ static u64 pmc_intel_save_disable_all(void)
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return ctrl;
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}
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-static u64 pmc_amd_save_disable_all(void)
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+static u64 amd_pmu_save_disable_all(void)
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{
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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int enabled, idx;
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@@ -327,7 +327,8 @@ static u64 pmc_amd_save_disable_all(void)
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cpuc->enabled = 0;
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/*
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* ensure we write the disable before we start disabling the
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- * counters proper, so that pcm_amd_enable() does the right thing.
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+ * counters proper, so that amd_pmu_enable_counter() does the
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+ * right thing.
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*/
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barrier();
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@@ -351,19 +352,19 @@ u64 hw_perf_save_disable(void)
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if (unlikely(!perf_counters_initialized))
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return 0;
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- return pmc_ops->save_disable_all();
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+ return x86_pmu->save_disable_all();
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}
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/*
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* Exported because of ACPI idle
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*/
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EXPORT_SYMBOL_GPL(hw_perf_save_disable);
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-static void pmc_intel_restore_all(u64 ctrl)
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+static void intel_pmu_restore_all(u64 ctrl)
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{
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wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
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}
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-static void pmc_amd_restore_all(u64 ctrl)
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+static void amd_pmu_restore_all(u64 ctrl)
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{
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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int idx;
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@@ -391,14 +392,14 @@ void hw_perf_restore(u64 ctrl)
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if (unlikely(!perf_counters_initialized))
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return;
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- pmc_ops->restore_all(ctrl);
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+ x86_pmu->restore_all(ctrl);
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}
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/*
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* Exported because of ACPI idle
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*/
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EXPORT_SYMBOL_GPL(hw_perf_restore);
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-static u64 pmc_intel_get_status(u64 mask)
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+static u64 intel_pmu_get_status(u64 mask)
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{
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u64 status;
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@@ -407,7 +408,7 @@ static u64 pmc_intel_get_status(u64 mask)
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return status;
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}
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-static u64 pmc_amd_get_status(u64 mask)
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+static u64 amd_pmu_get_status(u64 mask)
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{
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u64 status = 0;
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int idx;
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@@ -432,15 +433,15 @@ static u64 hw_perf_get_status(u64 mask)
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if (unlikely(!perf_counters_initialized))
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return 0;
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- return pmc_ops->get_status(mask);
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+ return x86_pmu->get_status(mask);
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}
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-static void pmc_intel_ack_status(u64 ack)
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+static void intel_pmu_ack_status(u64 ack)
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{
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wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
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}
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-static void pmc_amd_ack_status(u64 ack)
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+static void amd_pmu_ack_status(u64 ack)
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{
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}
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@@ -449,16 +450,16 @@ static void hw_perf_ack_status(u64 ack)
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if (unlikely(!perf_counters_initialized))
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return;
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- pmc_ops->ack_status(ack);
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+ x86_pmu->ack_status(ack);
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}
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-static void pmc_intel_enable(int idx, u64 config)
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+static void intel_pmu_enable_counter(int idx, u64 config)
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{
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wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx,
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config | ARCH_PERFMON_EVENTSEL0_ENABLE);
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}
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-static void pmc_amd_enable(int idx, u64 config)
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+static void amd_pmu_enable_counter(int idx, u64 config)
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{
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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@@ -474,15 +475,15 @@ static void hw_perf_enable(int idx, u64 config)
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if (unlikely(!perf_counters_initialized))
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return;
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- pmc_ops->enable(idx, config);
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+ x86_pmu->enable(idx, config);
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}
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-static void pmc_intel_disable(int idx, u64 config)
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+static void intel_pmu_disable_counter(int idx, u64 config)
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{
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wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + idx, config);
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}
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-static void pmc_amd_disable(int idx, u64 config)
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+static void amd_pmu_disable_counter(int idx, u64 config)
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{
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struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
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@@ -496,7 +497,7 @@ static void hw_perf_disable(int idx, u64 config)
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if (unlikely(!perf_counters_initialized))
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return;
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- pmc_ops->disable(idx, config);
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+ x86_pmu->disable(idx, config);
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}
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static inline void
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@@ -613,11 +614,11 @@ fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc)
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event = hwc->config & ARCH_PERFMON_EVENT_MASK;
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- if (unlikely(event == pmc_ops->event_map(PERF_COUNT_INSTRUCTIONS)))
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+ if (unlikely(event == x86_pmu->event_map(PERF_COUNT_INSTRUCTIONS)))
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return X86_PMC_IDX_FIXED_INSTRUCTIONS;
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- if (unlikely(event == pmc_ops->event_map(PERF_COUNT_CPU_CYCLES)))
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+ if (unlikely(event == x86_pmu->event_map(PERF_COUNT_CPU_CYCLES)))
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return X86_PMC_IDX_FIXED_CPU_CYCLES;
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- if (unlikely(event == pmc_ops->event_map(PERF_COUNT_BUS_CYCLES)))
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+ if (unlikely(event == x86_pmu->event_map(PERF_COUNT_BUS_CYCLES)))
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return X86_PMC_IDX_FIXED_BUS_CYCLES;
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return -1;
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@@ -661,8 +662,8 @@ try_generic:
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set_bit(idx, cpuc->used);
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hwc->idx = idx;
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}
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- hwc->config_base = pmc_ops->eventsel;
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- hwc->counter_base = pmc_ops->perfctr;
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+ hwc->config_base = x86_pmu->eventsel;
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+ hwc->counter_base = x86_pmu->perfctr;
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}
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perf_counters_lapic_init(hwc->nmi);
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@@ -710,8 +711,8 @@ void perf_counter_print_debug(void)
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pr_info("CPU#%d: used: %016llx\n", cpu, *(u64 *)cpuc->used);
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for (idx = 0; idx < nr_counters_generic; idx++) {
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- rdmsrl(pmc_ops->eventsel + idx, pmc_ctrl);
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- rdmsrl(pmc_ops->perfctr + idx, pmc_count);
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+ rdmsrl(x86_pmu->eventsel + idx, pmc_ctrl);
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+ rdmsrl(x86_pmu->perfctr + idx, pmc_count);
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prev_left = per_cpu(prev_left[idx], cpu);
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@@ -918,35 +919,35 @@ static __read_mostly struct notifier_block perf_counter_nmi_notifier = {
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.priority = 1
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};
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-static struct pmc_x86_ops pmc_intel_ops = {
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- .save_disable_all = pmc_intel_save_disable_all,
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- .restore_all = pmc_intel_restore_all,
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- .get_status = pmc_intel_get_status,
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- .ack_status = pmc_intel_ack_status,
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- .enable = pmc_intel_enable,
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- .disable = pmc_intel_disable,
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+static struct x86_pmu intel_pmu = {
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+ .save_disable_all = intel_pmu_save_disable_all,
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+ .restore_all = intel_pmu_restore_all,
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+ .get_status = intel_pmu_get_status,
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+ .ack_status = intel_pmu_ack_status,
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+ .enable = intel_pmu_enable_counter,
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+ .disable = intel_pmu_disable_counter,
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|
.eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
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.perfctr = MSR_ARCH_PERFMON_PERFCTR0,
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- .event_map = pmc_intel_event_map,
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|
- .raw_event = pmc_intel_raw_event,
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|
+ .event_map = intel_pmu_event_map,
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|
+ .raw_event = intel_pmu_raw_event,
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|
|
.max_events = ARRAY_SIZE(intel_perfmon_event_map),
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|
};
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|
|
|
|
-static struct pmc_x86_ops pmc_amd_ops = {
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|
- .save_disable_all = pmc_amd_save_disable_all,
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|
- .restore_all = pmc_amd_restore_all,
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- .get_status = pmc_amd_get_status,
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- .ack_status = pmc_amd_ack_status,
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- .enable = pmc_amd_enable,
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- .disable = pmc_amd_disable,
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|
|
+static struct x86_pmu amd_pmu = {
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+ .save_disable_all = amd_pmu_save_disable_all,
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+ .restore_all = amd_pmu_restore_all,
|
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+ .get_status = amd_pmu_get_status,
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+ .ack_status = amd_pmu_ack_status,
|
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|
+ .enable = amd_pmu_enable_counter,
|
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|
+ .disable = amd_pmu_disable_counter,
|
|
|
.eventsel = MSR_K7_EVNTSEL0,
|
|
|
.perfctr = MSR_K7_PERFCTR0,
|
|
|
- .event_map = pmc_amd_event_map,
|
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|
- .raw_event = pmc_amd_raw_event,
|
|
|
+ .event_map = amd_pmu_event_map,
|
|
|
+ .raw_event = amd_pmu_raw_event,
|
|
|
.max_events = ARRAY_SIZE(amd_perfmon_event_map),
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|
|
};
|
|
|
|
|
|
-static struct pmc_x86_ops *pmc_intel_init(void)
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|
|
+static struct x86_pmu *intel_pmu_init(void)
|
|
|
{
|
|
|
union cpuid10_edx edx;
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|
|
union cpuid10_eax eax;
|
|
@@ -977,10 +978,10 @@ static struct pmc_x86_ops *pmc_intel_init(void)
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|
|
nr_counters_fixed = edx.split.num_counters_fixed;
|
|
|
counter_value_mask = (1ULL << eax.split.bit_width) - 1;
|
|
|
|
|
|
- return &pmc_intel_ops;
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|
+ return &intel_pmu;
|
|
|
}
|
|
|
|
|
|
-static struct pmc_x86_ops *pmc_amd_init(void)
|
|
|
+static struct x86_pmu *amd_pmu_init(void)
|
|
|
{
|
|
|
nr_counters_generic = 4;
|
|
|
nr_counters_fixed = 0;
|
|
@@ -989,22 +990,22 @@ static struct pmc_x86_ops *pmc_amd_init(void)
|
|
|
|
|
|
pr_info("AMD Performance Monitoring support detected.\n");
|
|
|
|
|
|
- return &pmc_amd_ops;
|
|
|
+ return &amd_pmu;
|
|
|
}
|
|
|
|
|
|
void __init init_hw_perf_counters(void)
|
|
|
{
|
|
|
switch (boot_cpu_data.x86_vendor) {
|
|
|
case X86_VENDOR_INTEL:
|
|
|
- pmc_ops = pmc_intel_init();
|
|
|
+ x86_pmu = intel_pmu_init();
|
|
|
break;
|
|
|
case X86_VENDOR_AMD:
|
|
|
- pmc_ops = pmc_amd_init();
|
|
|
+ x86_pmu = amd_pmu_init();
|
|
|
break;
|
|
|
default:
|
|
|
return;
|
|
|
}
|
|
|
- if (!pmc_ops)
|
|
|
+ if (!x86_pmu)
|
|
|
return;
|
|
|
|
|
|
pr_info("... num counters: %d\n", nr_counters_generic);
|