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@@ -106,16 +106,26 @@ static int nr_channels;
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static int how_many_channels(struct pci_dev *pdev)
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{
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+ int n_channels;
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+
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unsigned char capid0_8b; /* 8th byte of CAPID0 */
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pci_read_config_byte(pdev, I3200_CAPID0 + 8, &capid0_8b);
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+
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if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */
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edac_dbg(0, "In single channel mode\n");
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- return 1;
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+ n_channels = 1;
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} else {
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edac_dbg(0, "In dual channel mode\n");
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- return 2;
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+ n_channels = 2;
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}
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+
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+ if (capid0_8b & 0x10) /* check if both channels are filled */
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+ edac_dbg(0, "2 DIMMS per channel disabled\n");
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+ else
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+ edac_dbg(0, "2 DIMMS per channel enabled\n");
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+
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+ return n_channels;
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}
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static unsigned long eccerrlog_syndrome(u64 log)
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@@ -290,6 +300,8 @@ static void i3200_get_drbs(void __iomem *window,
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for (i = 0; i < I3200_RANKS_PER_CHANNEL; i++) {
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drbs[0][i] = readw(window + I3200_C0DRB + 2*i) & I3200_DRB_MASK;
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drbs[1][i] = readw(window + I3200_C1DRB + 2*i) & I3200_DRB_MASK;
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+
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+ edac_dbg(0, "drb[0][%d] = %d, drb[1][%d] = %d\n", i, drbs[0][i], i, drbs[1][i]);
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}
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}
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