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@@ -75,7 +75,7 @@
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/* MSM specific */
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#define ABS_AHBBURST (0x0090UL)
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#define ABS_AHBMODE (0x0098UL)
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-/* UDC register map */
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+/* Controller register map */
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static uintptr_t ci_regs_nolpm[] = {
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[CAP_CAPLENGTH] = 0x000UL,
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[CAP_HCCPARAMS] = 0x008UL,
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@@ -88,6 +88,7 @@ static uintptr_t ci_regs_nolpm[] = {
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[OP_ENDPTLISTADDR] = 0x018UL,
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[OP_PORTSC] = 0x044UL,
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[OP_DEVLC] = 0x084UL,
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+ [OP_OTGSC] = 0x064UL,
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[OP_USBMODE] = 0x068UL,
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[OP_ENDPTSETUPSTAT] = 0x06CUL,
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[OP_ENDPTPRIME] = 0x070UL,
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@@ -109,6 +110,7 @@ static uintptr_t ci_regs_lpm[] = {
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[OP_ENDPTLISTADDR] = 0x018UL,
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[OP_PORTSC] = 0x044UL,
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[OP_DEVLC] = 0x084UL,
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+ [OP_OTGSC] = 0x0C4UL,
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[OP_USBMODE] = 0x0C8UL,
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[OP_ENDPTSETUPSTAT] = 0x0D8UL,
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[OP_ENDPTPRIME] = 0x0DCUL,
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@@ -118,24 +120,24 @@ static uintptr_t ci_regs_lpm[] = {
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[OP_ENDPTCTRL] = 0x0ECUL,
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};
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-static int hw_alloc_regmap(struct ci13xxx *udc, bool is_lpm)
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+static int hw_alloc_regmap(struct ci13xxx *ci, bool is_lpm)
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{
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int i;
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- kfree(udc->hw_bank.regmap);
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+ kfree(ci->hw_bank.regmap);
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- udc->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
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- GFP_KERNEL);
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- if (!udc->hw_bank.regmap)
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+ ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
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+ GFP_KERNEL);
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+ if (!ci->hw_bank.regmap)
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return -ENOMEM;
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for (i = 0; i < OP_ENDPTCTRL; i++)
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- udc->hw_bank.regmap[i] =
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- (i <= CAP_LAST ? udc->hw_bank.cap : udc->hw_bank.op) +
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+ ci->hw_bank.regmap[i] =
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+ (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
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(is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
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for (; i <= OP_LAST; i++)
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- udc->hw_bank.regmap[i] = udc->hw_bank.op +
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+ ci->hw_bank.regmap[i] = ci->hw_bank.op +
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4 * (i - OP_ENDPTCTRL) +
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(is_lpm
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? ci_regs_lpm[OP_ENDPTCTRL]
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@@ -171,36 +173,35 @@ u8 hw_port_test_get(struct ci13xxx *ci)
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return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
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}
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-int hw_device_init(struct ci13xxx *udc, void __iomem *base,
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- uintptr_t cap_offset)
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+static int hw_device_init(struct ci13xxx *ci, void __iomem *base)
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{
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u32 reg;
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/* bank is a module variable */
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- udc->hw_bank.abs = base;
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+ ci->hw_bank.abs = base;
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- udc->hw_bank.cap = udc->hw_bank.abs;
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- udc->hw_bank.cap += cap_offset;
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- udc->hw_bank.op = udc->hw_bank.cap + ioread8(udc->hw_bank.cap);
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+ ci->hw_bank.cap = ci->hw_bank.abs;
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+ ci->hw_bank.cap += ci->udc_driver->capoffset;
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+ ci->hw_bank.op = ci->hw_bank.cap + ioread8(ci->hw_bank.cap);
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- hw_alloc_regmap(udc, false);
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- reg = hw_read(udc, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
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+ hw_alloc_regmap(ci, false);
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+ reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
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ffs_nr(HCCPARAMS_LEN);
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- udc->hw_bank.lpm = reg;
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- hw_alloc_regmap(udc, !!reg);
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- udc->hw_bank.size = udc->hw_bank.op - udc->hw_bank.abs;
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- udc->hw_bank.size += OP_LAST;
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- udc->hw_bank.size /= sizeof(u32);
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+ ci->hw_bank.lpm = reg;
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+ hw_alloc_regmap(ci, !!reg);
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+ ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
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+ ci->hw_bank.size += OP_LAST;
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+ ci->hw_bank.size /= sizeof(u32);
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- reg = hw_read(udc, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
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+ reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
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ffs_nr(DCCPARAMS_DEN);
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- udc->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
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+ ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
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- if (udc->hw_ep_max == 0 || udc->hw_ep_max > ENDPT_MAX)
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+ if (ci->hw_ep_max == 0 || ci->hw_ep_max > ENDPT_MAX)
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return -ENODEV;
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- dev_dbg(udc->dev, "ChipIdea UDC found, lpm: %d; cap: %p op: %p\n",
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- udc->hw_bank.lpm, udc->hw_bank.cap, udc->hw_bank.op);
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+ dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
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+ ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
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/* setup lock mode ? */
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@@ -250,16 +251,98 @@ int hw_device_reset(struct ci13xxx *ci)
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return 0;
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}
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-static int __devinit ci_udc_probe(struct platform_device *pdev)
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+/**
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+ * ci_otg_role - pick role based on ID pin state
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+ * @ci: the controller
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+ */
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+static enum ci_role ci_otg_role(struct ci13xxx *ci)
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+{
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+ u32 sts = hw_read(ci, OP_OTGSC, ~0);
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+ enum ci_role role = sts & OTGSC_ID
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+ ? CI_ROLE_GADGET
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+ : CI_ROLE_HOST;
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+
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+ return role;
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+}
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+
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+/**
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+ * ci_role_work - perform role changing based on ID pin
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+ * @work: work struct
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+ */
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+static void ci_role_work(struct work_struct *work)
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+{
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+ struct ci13xxx *ci = container_of(work, struct ci13xxx, work);
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+ enum ci_role role = ci_otg_role(ci);
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+
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+ hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);
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+
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+ if (role != ci->role) {
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+ dev_dbg(ci->dev, "switching from %s to %s\n",
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+ ci_role(ci)->name, ci->roles[role]->name);
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+
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+ ci_role_stop(ci);
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+ ci_role_start(ci, role);
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+ }
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+}
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+
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+static ssize_t show_role(struct device *dev, struct device_attribute *attr,
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+ char *buf)
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+{
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+ struct ci13xxx *ci = dev_get_drvdata(dev);
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+
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+ return sprintf(buf, "%s\n", ci_role(ci)->name);
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+}
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+
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+static ssize_t store_role(struct device *dev, struct device_attribute *attr,
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+ const char *buf, size_t count)
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+{
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+ struct ci13xxx *ci = dev_get_drvdata(dev);
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+ enum ci_role role;
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+ int ret;
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+
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+ for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
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+ if (ci->roles[role] && !strcmp(buf, ci->roles[role]->name))
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+ break;
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+
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+ if (role == CI_ROLE_END || role == ci->role)
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+ return -EINVAL;
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+
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+ ci_role_stop(ci);
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+ ret = ci_role_start(ci, role);
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+ if (ret)
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+ return ret;
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+
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+ return count;
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+}
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+
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+static DEVICE_ATTR(role, S_IRUSR | S_IWUSR, show_role, store_role);
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+
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+static irqreturn_t ci_irq(int irq, void *data)
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+{
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+ struct ci13xxx *ci = data;
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+ irqreturn_t ret = IRQ_NONE;
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+
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+ if (ci->is_otg) {
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+ u32 sts = hw_read(ci, OP_OTGSC, ~0);
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+
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+ if (sts & OTGSC_IDIS) {
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+ queue_work(ci->wq, &ci->work);
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+ ret = IRQ_HANDLED;
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+ }
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+ }
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+
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+ return ci->role == CI_ROLE_END ? ret : ci_role(ci)->irq(ci);
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+}
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+
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+static int __devinit ci_hdrc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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- struct ci13xxx_udc_driver *driver = dev->platform_data;
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- struct ci13xxx *udc;
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+ struct ci13xxx *ci;
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struct resource *res;
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void __iomem *base;
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int ret;
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- if (!driver) {
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+ if (!dev->platform_data) {
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dev_err(dev, "platform data missing\n");
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return -ENODEV;
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}
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@@ -276,49 +359,112 @@ static int __devinit ci_udc_probe(struct platform_device *pdev)
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return -ENOMEM;
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}
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- ret = udc_probe(driver, dev, base, &udc);
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- if (ret)
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- return ret;
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+ ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
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+ if (!ci) {
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+ dev_err(dev, "can't allocate device\n");
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+ return -ENOMEM;
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+ }
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+
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+ ci->dev = dev;
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+ ci->udc_driver = dev->platform_data;
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+
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+ ret = hw_device_init(ci, base);
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+ if (ret < 0) {
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+ dev_err(dev, "can't initialize hardware\n");
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+ return -ENODEV;
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+ }
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- udc->irq = platform_get_irq(pdev, 0);
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- if (udc->irq < 0) {
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+ ci->irq = platform_get_irq(pdev, 0);
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+ if (ci->irq < 0) {
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dev_err(dev, "missing IRQ\n");
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+ return -ENODEV;
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+ }
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+
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+ INIT_WORK(&ci->work, ci_role_work);
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+ ci->wq = create_singlethread_workqueue("ci_otg");
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+ if (!ci->wq) {
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+ dev_err(dev, "can't create workqueue\n");
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+ return -ENODEV;
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+ }
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+
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+ /* initialize role(s) before the interrupt is requested */
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+ ret = ci_hdrc_gadget_init(ci);
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+ if (ret)
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+ dev_info(dev, "doesn't support gadget\n");
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+
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+ if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
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+ dev_err(dev, "no supported roles\n");
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+ ret = -ENODEV;
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+ goto rm_wq;
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+ }
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+
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+ if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
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+ ci->is_otg = true;
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+ ci->role = ci_otg_role(ci);
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+ } else {
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+ ci->role = ci->roles[CI_ROLE_HOST]
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+ ? CI_ROLE_HOST
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+ : CI_ROLE_GADGET;
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+ }
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+
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+ ret = ci_role_start(ci, ci->role);
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+ if (ret) {
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+ dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
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ret = -ENODEV;
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- goto out;
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+ goto rm_wq;
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}
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- platform_set_drvdata(pdev, udc);
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- ret = request_irq(udc->irq, udc_irq, IRQF_SHARED, driver->name, udc);
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+ platform_set_drvdata(pdev, ci);
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+ ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->udc_driver->name,
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+ ci);
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+ if (ret)
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+ goto stop;
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-out:
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+ ret = device_create_file(dev, &dev_attr_role);
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if (ret)
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- udc_remove(udc);
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+ goto rm_attr;
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+
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+ if (ci->is_otg)
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+ hw_write(ci, OP_OTGSC, OTGSC_IDIE, OTGSC_IDIE);
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+
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+ return ret;
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+
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+rm_attr:
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+ device_remove_file(dev, &dev_attr_role);
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+stop:
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+ ci_role_stop(ci);
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+rm_wq:
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+ flush_workqueue(ci->wq);
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+ destroy_workqueue(ci->wq);
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return ret;
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}
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-static int __devexit ci_udc_remove(struct platform_device *pdev)
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+static int __devexit ci_hdrc_remove(struct platform_device *pdev)
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{
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- struct ci13xxx *udc = platform_get_drvdata(pdev);
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+ struct ci13xxx *ci = platform_get_drvdata(pdev);
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- free_irq(udc->irq, udc);
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- udc_remove(udc);
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+ flush_workqueue(ci->wq);
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+ destroy_workqueue(ci->wq);
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+ device_remove_file(ci->dev, &dev_attr_role);
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+ free_irq(ci->irq, ci);
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+ ci_role_stop(ci);
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return 0;
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}
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-static struct platform_driver ci_udc_driver = {
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- .probe = ci_udc_probe,
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- .remove = __devexit_p(ci_udc_remove),
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+static struct platform_driver ci_hdrc_driver = {
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+ .probe = ci_hdrc_probe,
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+ .remove = __devexit_p(ci_hdrc_remove),
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.driver = {
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- .name = "ci_udc",
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+ .name = "ci_hdrc",
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},
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};
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-module_platform_driver(ci_udc_driver);
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+module_platform_driver(ci_hdrc_driver);
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-MODULE_ALIAS("platform:ci_udc");
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+MODULE_ALIAS("platform:ci_hdrc");
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MODULE_ALIAS("platform:ci13xxx");
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
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-MODULE_DESCRIPTION("ChipIdea UDC Driver");
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+MODULE_DESCRIPTION("ChipIdea HDRC Driver");
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