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@@ -12527,6 +12527,7 @@ int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
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vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
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vars->mac_type = MAC_TYPE_NONE;
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vars->phy_flags = 0;
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+ vars->check_kr2_recovery_cnt = 0;
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/* Driver opens NIG-BRB filters */
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bnx2x_set_rx_filter(params, 1);
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/* Check if link flap can be avoided */
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@@ -13411,6 +13412,7 @@ static void bnx2x_disable_kr2(struct link_params *params,
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vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
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bnx2x_update_link_attr(params, vars->link_attr_sync);
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+ vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;
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/* Restart AN on leading lane */
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bnx2x_warpcore_restart_AN_KR(phy, params);
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}
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@@ -13439,6 +13441,15 @@ static void bnx2x_check_kr2_wa(struct link_params *params,
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return;
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}
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+ /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
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+ * since some switches tend to reinit the AN process and clear the
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+ * advertised BP/NP after ~2 seconds causing the KR2 to be disabled
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+ * and recovered many times
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+ */
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+ if (vars->check_kr2_recovery_cnt > 0) {
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+ vars->check_kr2_recovery_cnt--;
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+ return;
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+ }
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lane = bnx2x_get_warpcore_lane(phy, params);
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CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
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MDIO_AER_BLOCK_AER_REG, lane);
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