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@@ -199,7 +199,6 @@ ENTRY(flush_instruction_cache_local)
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.callinfo NO_CALLS
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.entry
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- mtsp %r0, %sr1
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load32 cache_info, %r1
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/* Flush Instruction Cache */
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@@ -208,7 +207,8 @@ ENTRY(flush_instruction_cache_local)
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LDREG ICACHE_STRIDE(%r1), %arg1
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LDREG ICACHE_COUNT(%r1), %arg2
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LDREG ICACHE_LOOP(%r1), %arg3
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- rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/
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+ rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/
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+ mtsp %r0, %sr1
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addib,COND(=) -1, %arg3, fioneloop /* Preadjust and test */
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movb,<,n %arg3, %r31, fisync /* If loop < 0, do sync */
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@@ -220,7 +220,33 @@ fimanyloop: /* Loop if LOOP >= 2 */
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addib,COND(<=),n -1, %arg2, fisync /* Outer loop decr */
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fioneloop: /* Loop if LOOP = 1 */
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- addib,COND(>) -1, %arg2, fioneloop /* Outer loop count decr */
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+ /* Some implementations may flush with a single fice instruction */
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+ cmpib,COND(>>=),n 15, %arg2, fioneloop2
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+
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+fioneloop1:
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+ fice,m %arg1(%sr1, %arg0)
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+ fice,m %arg1(%sr1, %arg0)
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+ fice,m %arg1(%sr1, %arg0)
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+ fice,m %arg1(%sr1, %arg0)
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+ fice,m %arg1(%sr1, %arg0)
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+ fice,m %arg1(%sr1, %arg0)
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+ fice,m %arg1(%sr1, %arg0)
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+ fice,m %arg1(%sr1, %arg0)
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+ fice,m %arg1(%sr1, %arg0)
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+ fice,m %arg1(%sr1, %arg0)
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+ fice,m %arg1(%sr1, %arg0)
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+ fice,m %arg1(%sr1, %arg0)
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+ fice,m %arg1(%sr1, %arg0)
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+ fice,m %arg1(%sr1, %arg0)
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+ fice,m %arg1(%sr1, %arg0)
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+ addib,COND(>) -16, %arg2, fioneloop1
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+ fice,m %arg1(%sr1, %arg0)
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+
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+ /* Check if done */
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+ cmpb,COND(=),n %arg2, %r0, fisync /* Predict branch taken */
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+
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+fioneloop2:
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+ addib,COND(>) -1, %arg2, fioneloop2 /* Outer loop count decr */
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fice,m %arg1(%sr1, %arg0) /* Fice for one loop */
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fisync:
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@@ -240,8 +266,7 @@ ENTRY(flush_data_cache_local)
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.callinfo NO_CALLS
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.entry
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- mtsp %r0, %sr1
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- load32 cache_info, %r1
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+ load32 cache_info, %r1
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/* Flush Data Cache */
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@@ -249,7 +274,8 @@ ENTRY(flush_data_cache_local)
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LDREG DCACHE_STRIDE(%r1), %arg1
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LDREG DCACHE_COUNT(%r1), %arg2
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LDREG DCACHE_LOOP(%r1), %arg3
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- rsm PSW_SM_I, %r22
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+ rsm PSW_SM_I, %r22 /* No mmgt ops during loop*/
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+ mtsp %r0, %sr1
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addib,COND(=) -1, %arg3, fdoneloop /* Preadjust and test */
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movb,<,n %arg3, %r31, fdsync /* If loop < 0, do sync */
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@@ -261,7 +287,33 @@ fdmanyloop: /* Loop if LOOP >= 2 */
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addib,COND(<=),n -1, %arg2, fdsync /* Outer loop decr */
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fdoneloop: /* Loop if LOOP = 1 */
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- addib,COND(>) -1, %arg2, fdoneloop /* Outer loop count decr */
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+ /* Some implementations may flush with a single fdce instruction */
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+ cmpib,COND(>>=),n 15, %arg2, fdoneloop2
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+
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+fdoneloop1:
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+ fdce,m %arg1(%sr1, %arg0)
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+ fdce,m %arg1(%sr1, %arg0)
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+ fdce,m %arg1(%sr1, %arg0)
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+ fdce,m %arg1(%sr1, %arg0)
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+ fdce,m %arg1(%sr1, %arg0)
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+ fdce,m %arg1(%sr1, %arg0)
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+ fdce,m %arg1(%sr1, %arg0)
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+ fdce,m %arg1(%sr1, %arg0)
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+ fdce,m %arg1(%sr1, %arg0)
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+ fdce,m %arg1(%sr1, %arg0)
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+ fdce,m %arg1(%sr1, %arg0)
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+ fdce,m %arg1(%sr1, %arg0)
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+ fdce,m %arg1(%sr1, %arg0)
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+ fdce,m %arg1(%sr1, %arg0)
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+ fdce,m %arg1(%sr1, %arg0)
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+ addib,COND(>) -16, %arg2, fdoneloop1
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+ fdce,m %arg1(%sr1, %arg0)
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+
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+ /* Check if done */
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+ cmpb,COND(=),n %arg2, %r0, fdsync /* Predict branch taken */
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+
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+fdoneloop2:
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+ addib,COND(>) -1, %arg2, fdoneloop2 /* Outer loop count decr */
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fdce,m %arg1(%sr1, %arg0) /* Fdce for one loop */
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fdsync:
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@@ -277,7 +329,104 @@ ENDPROC(flush_data_cache_local)
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.align 16
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-ENTRY(copy_user_page_asm)
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+/* Macros to serialize TLB purge operations on SMP. */
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+
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+ .macro tlb_lock la,flags,tmp
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+#ifdef CONFIG_SMP
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+ ldil L%pa_tlb_lock,%r1
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+ ldo R%pa_tlb_lock(%r1),\la
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+ rsm PSW_SM_I,\flags
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+1: LDCW 0(\la),\tmp
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+ cmpib,<>,n 0,\tmp,3f
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+2: ldw 0(\la),\tmp
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+ cmpb,<> %r0,\tmp,1b
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+ nop
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+ b,n 2b
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+3:
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+#endif
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+ .endm
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+
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+ .macro tlb_unlock la,flags,tmp
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+#ifdef CONFIG_SMP
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+ ldi 1,\tmp
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+ stw \tmp,0(\la)
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+ mtsm \flags
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+#endif
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+ .endm
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+
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+/* Clear page using kernel mapping. */
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+
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+ENTRY(clear_page_asm)
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+ .proc
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+ .callinfo NO_CALLS
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+ .entry
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+
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+#ifdef CONFIG_64BIT
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+
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+ /* Unroll the loop. */
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+ ldi (PAGE_SIZE / 128), %r1
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+
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+1:
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+ std %r0, 0(%r26)
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+ std %r0, 8(%r26)
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+ std %r0, 16(%r26)
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+ std %r0, 24(%r26)
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+ std %r0, 32(%r26)
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+ std %r0, 40(%r26)
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+ std %r0, 48(%r26)
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+ std %r0, 56(%r26)
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+ std %r0, 64(%r26)
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+ std %r0, 72(%r26)
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+ std %r0, 80(%r26)
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+ std %r0, 88(%r26)
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+ std %r0, 96(%r26)
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+ std %r0, 104(%r26)
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+ std %r0, 112(%r26)
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+ std %r0, 120(%r26)
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+
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+ /* Note reverse branch hint for addib is taken. */
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+ addib,COND(>),n -1, %r1, 1b
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+ ldo 128(%r26), %r26
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+
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+#else
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+
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+ /*
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+ * Note that until (if) we start saving the full 64-bit register
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+ * values on interrupt, we can't use std on a 32 bit kernel.
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+ */
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+ ldi (PAGE_SIZE / 64), %r1
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+
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+1:
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+ stw %r0, 0(%r26)
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+ stw %r0, 4(%r26)
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+ stw %r0, 8(%r26)
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+ stw %r0, 12(%r26)
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+ stw %r0, 16(%r26)
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+ stw %r0, 20(%r26)
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+ stw %r0, 24(%r26)
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+ stw %r0, 28(%r26)
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+ stw %r0, 32(%r26)
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+ stw %r0, 36(%r26)
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+ stw %r0, 40(%r26)
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+ stw %r0, 44(%r26)
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+ stw %r0, 48(%r26)
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+ stw %r0, 52(%r26)
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+ stw %r0, 56(%r26)
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+ stw %r0, 60(%r26)
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+
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+ addib,COND(>),n -1, %r1, 1b
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+ ldo 64(%r26), %r26
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+#endif
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+ bv %r0(%r2)
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+ nop
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+ .exit
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+
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+ .procend
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+ENDPROC(clear_page_asm)
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+
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+/* Copy page using kernel mapping. */
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+
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+ENTRY(copy_page_asm)
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.proc
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.callinfo NO_CALLS
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.entry
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@@ -285,18 +434,14 @@ ENTRY(copy_user_page_asm)
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#ifdef CONFIG_64BIT
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/* PA8x00 CPUs can consume 2 loads or 1 store per cycle.
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* Unroll the loop by hand and arrange insn appropriately.
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- * GCC probably can do this just as well.
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+ * Prefetch doesn't improve performance on rp3440.
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+ * GCC probably can do this just as well...
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*/
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- ldd 0(%r25), %r19
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ldi (PAGE_SIZE / 128), %r1
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- ldw 64(%r25), %r0 /* prefetch 1 cacheline ahead */
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- ldw 128(%r25), %r0 /* prefetch 2 */
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-
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-1: ldd 8(%r25), %r20
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- ldw 192(%r25), %r0 /* prefetch 3 */
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- ldw 256(%r25), %r0 /* prefetch 4 */
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+1: ldd 0(%r25), %r19
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+ ldd 8(%r25), %r20
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ldd 16(%r25), %r21
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ldd 24(%r25), %r22
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@@ -330,20 +475,16 @@ ENTRY(copy_user_page_asm)
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ldd 112(%r25), %r21
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ldd 120(%r25), %r22
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+ ldo 128(%r25), %r25
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std %r19, 96(%r26)
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std %r20, 104(%r26)
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- ldo 128(%r25), %r25
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std %r21, 112(%r26)
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std %r22, 120(%r26)
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- ldo 128(%r26), %r26
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- /* conditional branches nullify on forward taken branch, and on
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- * non-taken backward branch. Note that .+4 is a backwards branch.
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- * The ldd should only get executed if the branch is taken.
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- */
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- addib,COND(>),n -1, %r1, 1b /* bundle 10 */
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- ldd 0(%r25), %r19 /* start next loads */
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+ /* Note reverse branch hint for addib is taken. */
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+ addib,COND(>),n -1, %r1, 1b
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+ ldo 128(%r26), %r26
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#else
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@@ -399,7 +540,7 @@ ENTRY(copy_user_page_asm)
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.exit
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.procend
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-ENDPROC(copy_user_page_asm)
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+ENDPROC(copy_page_asm)
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/*
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* NOTE: Code in clear_user_page has a hard coded dependency on the
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@@ -422,8 +563,6 @@ ENDPROC(copy_user_page_asm)
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* %r23 physical page (shifted for tlb insert) of "from" translation
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*/
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-#if 0
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-
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/*
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* We can't do this since copy_user_page is used to bring in
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* file data that might have instructions. Since the data would
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@@ -435,6 +574,7 @@ ENDPROC(copy_user_page_asm)
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* use it if more information is passed into copy_user_page().
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* Have to do some measurements to see if it is worthwhile to
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* lobby for such a change.
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+ *
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*/
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ENTRY(copy_user_page_asm)
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@@ -442,16 +582,21 @@ ENTRY(copy_user_page_asm)
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.callinfo NO_CALLS
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.entry
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+ /* Convert virtual `to' and `from' addresses to physical addresses.
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+ Move `from' physical address to non shadowed register. */
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ldil L%(__PAGE_OFFSET), %r1
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sub %r26, %r1, %r26
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- sub %r25, %r1, %r23 /* move physical addr into non shadowed reg */
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+ sub %r25, %r1, %r23
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ldil L%(TMPALIAS_MAP_START), %r28
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/* FIXME for different page sizes != 4k */
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#ifdef CONFIG_64BIT
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- extrd,u %r26,56,32, %r26 /* convert phys addr to tlb insert format */
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- extrd,u %r23,56,32, %r23 /* convert phys addr to tlb insert format */
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- depd %r24,63,22, %r28 /* Form aliased virtual address 'to' */
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+#if (TMPALIAS_MAP_START >= 0x80000000)
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+ depdi 0, 31,32, %r28 /* clear any sign extension */
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+#endif
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+ extrd,u %r26,56,32, %r26 /* convert phys addr to tlb insert format */
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+ extrd,u %r23,56,32, %r23 /* convert phys addr to tlb insert format */
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+ depd %r24,63,22, %r28 /* Form aliased virtual address 'to' */
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depdi 0, 63,12, %r28 /* Clear any offset bits */
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copy %r28, %r29
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depdi 1, 41,1, %r29 /* Form aliased virtual address 'from' */
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@@ -466,10 +611,76 @@ ENTRY(copy_user_page_asm)
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/* Purge any old translations */
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+#ifdef CONFIG_PA20
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+ pdtlb,l 0(%r28)
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+ pdtlb,l 0(%r29)
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+#else
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+ tlb_lock %r20,%r21,%r22
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pdtlb 0(%r28)
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pdtlb 0(%r29)
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+ tlb_unlock %r20,%r21,%r22
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+#endif
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+
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+#ifdef CONFIG_64BIT
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+ /* PA8x00 CPUs can consume 2 loads or 1 store per cycle.
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+ * Unroll the loop by hand and arrange insn appropriately.
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+ * GCC probably can do this just as well.
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+ */
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- ldi 64, %r1
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+ ldd 0(%r29), %r19
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+ ldi (PAGE_SIZE / 128), %r1
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+
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+1: ldd 8(%r29), %r20
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+
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+ ldd 16(%r29), %r21
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+ ldd 24(%r29), %r22
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+ std %r19, 0(%r28)
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+ std %r20, 8(%r28)
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+
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+ ldd 32(%r29), %r19
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+ ldd 40(%r29), %r20
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+ std %r21, 16(%r28)
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+ std %r22, 24(%r28)
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+
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+ ldd 48(%r29), %r21
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+ ldd 56(%r29), %r22
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+ std %r19, 32(%r28)
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+ std %r20, 40(%r28)
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+
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+ ldd 64(%r29), %r19
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+ ldd 72(%r29), %r20
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+ std %r21, 48(%r28)
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+ std %r22, 56(%r28)
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+
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+ ldd 80(%r29), %r21
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+ ldd 88(%r29), %r22
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+ std %r19, 64(%r28)
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+ std %r20, 72(%r28)
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+
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+ ldd 96(%r29), %r19
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+ ldd 104(%r29), %r20
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+ std %r21, 80(%r28)
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+ std %r22, 88(%r28)
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+
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+ ldd 112(%r29), %r21
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+ ldd 120(%r29), %r22
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+ std %r19, 96(%r28)
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+ std %r20, 104(%r28)
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+
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+ ldo 128(%r29), %r29
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+ std %r21, 112(%r28)
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+ std %r22, 120(%r28)
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+ ldo 128(%r28), %r28
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+
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+ /* conditional branches nullify on forward taken branch, and on
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+ * non-taken backward branch. Note that .+4 is a backwards branch.
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+ * The ldd should only get executed if the branch is taken.
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+ */
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+ addib,COND(>),n -1, %r1, 1b /* bundle 10 */
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+ ldd 0(%r29), %r19 /* start next loads */
|
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+
|
|
|
+#else
|
|
|
+ ldi (PAGE_SIZE / 64), %r1
|
|
|
|
|
|
/*
|
|
|
* This loop is optimized for PCXL/PCXL2 ldw/ldw and stw/stw
|
|
@@ -480,9 +691,7 @@ ENTRY(copy_user_page_asm)
|
|
|
* use ldd/std on a 32 bit kernel.
|
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|
*/
|
|
|
|
|
|
-
|
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-1:
|
|
|
- ldw 0(%r29), %r19
|
|
|
+1: ldw 0(%r29), %r19
|
|
|
ldw 4(%r29), %r20
|
|
|
ldw 8(%r29), %r21
|
|
|
ldw 12(%r29), %r22
|
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@@ -515,8 +724,10 @@ ENTRY(copy_user_page_asm)
|
|
|
stw %r21, 56(%r28)
|
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|
stw %r22, 60(%r28)
|
|
|
ldo 64(%r28), %r28
|
|
|
+
|
|
|
addib,COND(>) -1, %r1,1b
|
|
|
ldo 64(%r29), %r29
|
|
|
+#endif
|
|
|
|
|
|
bv %r0(%r2)
|
|
|
nop
|
|
@@ -524,9 +735,8 @@ ENTRY(copy_user_page_asm)
|
|
|
|
|
|
.procend
|
|
|
ENDPROC(copy_user_page_asm)
|
|
|
-#endif
|
|
|
|
|
|
-ENTRY(__clear_user_page_asm)
|
|
|
+ENTRY(clear_user_page_asm)
|
|
|
.proc
|
|
|
.callinfo NO_CALLS
|
|
|
.entry
|
|
@@ -550,7 +760,13 @@ ENTRY(__clear_user_page_asm)
|
|
|
|
|
|
/* Purge any old translation */
|
|
|
|
|
|
+#ifdef CONFIG_PA20
|
|
|
+ pdtlb,l 0(%r28)
|
|
|
+#else
|
|
|
+ tlb_lock %r20,%r21,%r22
|
|
|
pdtlb 0(%r28)
|
|
|
+ tlb_unlock %r20,%r21,%r22
|
|
|
+#endif
|
|
|
|
|
|
#ifdef CONFIG_64BIT
|
|
|
ldi (PAGE_SIZE / 128), %r1
|
|
@@ -580,8 +796,7 @@ ENTRY(__clear_user_page_asm)
|
|
|
#else /* ! CONFIG_64BIT */
|
|
|
ldi (PAGE_SIZE / 64), %r1
|
|
|
|
|
|
-1:
|
|
|
- stw %r0, 0(%r28)
|
|
|
+1: stw %r0, 0(%r28)
|
|
|
stw %r0, 4(%r28)
|
|
|
stw %r0, 8(%r28)
|
|
|
stw %r0, 12(%r28)
|
|
@@ -606,7 +821,7 @@ ENTRY(__clear_user_page_asm)
|
|
|
.exit
|
|
|
|
|
|
.procend
|
|
|
-ENDPROC(__clear_user_page_asm)
|
|
|
+ENDPROC(clear_user_page_asm)
|
|
|
|
|
|
ENTRY(flush_dcache_page_asm)
|
|
|
.proc
|
|
@@ -630,7 +845,13 @@ ENTRY(flush_dcache_page_asm)
|
|
|
|
|
|
/* Purge any old translation */
|
|
|
|
|
|
+#ifdef CONFIG_PA20
|
|
|
+ pdtlb,l 0(%r28)
|
|
|
+#else
|
|
|
+ tlb_lock %r20,%r21,%r22
|
|
|
pdtlb 0(%r28)
|
|
|
+ tlb_unlock %r20,%r21,%r22
|
|
|
+#endif
|
|
|
|
|
|
ldil L%dcache_stride, %r1
|
|
|
ldw R%dcache_stride(%r1), %r1
|
|
@@ -663,8 +884,17 @@ ENTRY(flush_dcache_page_asm)
|
|
|
fdc,m %r1(%r28)
|
|
|
|
|
|
sync
|
|
|
+
|
|
|
+#ifdef CONFIG_PA20
|
|
|
+ pdtlb,l 0(%r25)
|
|
|
+#else
|
|
|
+ tlb_lock %r20,%r21,%r22
|
|
|
+ pdtlb 0(%r25)
|
|
|
+ tlb_unlock %r20,%r21,%r22
|
|
|
+#endif
|
|
|
+
|
|
|
bv %r0(%r2)
|
|
|
- pdtlb (%r25)
|
|
|
+ nop
|
|
|
.exit
|
|
|
|
|
|
.procend
|
|
@@ -692,7 +922,13 @@ ENTRY(flush_icache_page_asm)
|
|
|
|
|
|
/* Purge any old translation */
|
|
|
|
|
|
- pitlb (%sr4,%r28)
|
|
|
+#ifdef CONFIG_PA20
|
|
|
+ pitlb,l %r0(%sr4,%r28)
|
|
|
+#else
|
|
|
+ tlb_lock %r20,%r21,%r22
|
|
|
+ pitlb (%sr4,%r28)
|
|
|
+ tlb_unlock %r20,%r21,%r22
|
|
|
+#endif
|
|
|
|
|
|
ldil L%icache_stride, %r1
|
|
|
ldw R%icache_stride(%r1), %r1
|
|
@@ -727,8 +963,17 @@ ENTRY(flush_icache_page_asm)
|
|
|
fic,m %r1(%sr4,%r28)
|
|
|
|
|
|
sync
|
|
|
+
|
|
|
+#ifdef CONFIG_PA20
|
|
|
+ pitlb,l %r0(%sr4,%r25)
|
|
|
+#else
|
|
|
+ tlb_lock %r20,%r21,%r22
|
|
|
+ pitlb (%sr4,%r25)
|
|
|
+ tlb_unlock %r20,%r21,%r22
|
|
|
+#endif
|
|
|
+
|
|
|
bv %r0(%r2)
|
|
|
- pitlb (%sr4,%r25)
|
|
|
+ nop
|
|
|
.exit
|
|
|
|
|
|
.procend
|
|
@@ -777,7 +1022,7 @@ ENTRY(flush_kernel_dcache_page_asm)
|
|
|
.procend
|
|
|
ENDPROC(flush_kernel_dcache_page_asm)
|
|
|
|
|
|
-ENTRY(purge_kernel_dcache_page)
|
|
|
+ENTRY(purge_kernel_dcache_page_asm)
|
|
|
.proc
|
|
|
.callinfo NO_CALLS
|
|
|
.entry
|
|
@@ -817,7 +1062,7 @@ ENTRY(purge_kernel_dcache_page)
|
|
|
.exit
|
|
|
|
|
|
.procend
|
|
|
-ENDPROC(purge_kernel_dcache_page)
|
|
|
+ENDPROC(purge_kernel_dcache_page_asm)
|
|
|
|
|
|
ENTRY(flush_user_dcache_range_asm)
|
|
|
.proc
|