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+/*
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+ * Copyright (c) 2010-2011 Picochip Ltd., Jamie Iles
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * All enquiries to support@picochip.com
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+ */
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+#include <linux/clk.h>
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+#include <linux/delay.h>
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+#include <linux/err.h>
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+#include <linux/hw_random.h>
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+#include <linux/io.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+
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+#define DATA_REG_OFFSET 0x0200
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+#define CSR_REG_OFFSET 0x0278
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+#define CSR_OUT_EMPTY_MASK (1 << 24)
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+#define CSR_FAULT_MASK (1 << 1)
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+#define TRNG_BLOCK_RESET_MASK (1 << 0)
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+#define TAI_REG_OFFSET 0x0380
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+
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+/*
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+ * The maximum amount of time in microseconds to spend waiting for data if the
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+ * core wants us to wait. The TRNG should generate 32 bits every 320ns so a
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+ * timeout of 20us seems reasonable. The TRNG does builtin tests of the data
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+ * for randomness so we can't always assume there is data present.
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+ */
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+#define PICO_TRNG_TIMEOUT 20
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+
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+static void __iomem *rng_base;
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+static struct clk *rng_clk;
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+struct device *rng_dev;
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+
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+static inline u32 picoxcell_trng_read_csr(void)
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+{
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+ return __raw_readl(rng_base + CSR_REG_OFFSET);
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+}
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+
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+static inline bool picoxcell_trng_is_empty(void)
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+{
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+ return picoxcell_trng_read_csr() & CSR_OUT_EMPTY_MASK;
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+}
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+
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+/*
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+ * Take the random number generator out of reset and make sure the interrupts
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+ * are masked. We shouldn't need to get large amounts of random bytes so just
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+ * poll the status register. The hardware generates 32 bits every 320ns so we
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+ * shouldn't have to wait long enough to warrant waiting for an IRQ.
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+ */
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+static void picoxcell_trng_start(void)
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+{
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+ __raw_writel(0, rng_base + TAI_REG_OFFSET);
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+ __raw_writel(0, rng_base + CSR_REG_OFFSET);
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+}
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+
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+static void picoxcell_trng_reset(void)
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+{
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+ __raw_writel(TRNG_BLOCK_RESET_MASK, rng_base + CSR_REG_OFFSET);
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+ __raw_writel(TRNG_BLOCK_RESET_MASK, rng_base + TAI_REG_OFFSET);
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+ picoxcell_trng_start();
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+}
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+
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+/*
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+ * Get some random data from the random number generator. The hw_random core
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+ * layer provides us with locking.
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+ */
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+static int picoxcell_trng_read(struct hwrng *rng, void *buf, size_t max,
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+ bool wait)
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+{
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+ int i;
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+
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+ /* Wait for some data to become available. */
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+ for (i = 0; i < PICO_TRNG_TIMEOUT && picoxcell_trng_is_empty(); ++i) {
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+ if (!wait)
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+ return 0;
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+
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+ udelay(1);
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+ }
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+
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+ if (picoxcell_trng_read_csr() & CSR_FAULT_MASK) {
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+ dev_err(rng_dev, "fault detected, resetting TRNG\n");
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+ picoxcell_trng_reset();
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+ return -EIO;
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+ }
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+
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+ if (i == PICO_TRNG_TIMEOUT)
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+ return 0;
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+
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+ *(u32 *)buf = __raw_readl(rng_base + DATA_REG_OFFSET);
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+ return sizeof(u32);
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+}
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+
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+static struct hwrng picoxcell_trng = {
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+ .name = "picoxcell",
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+ .read = picoxcell_trng_read,
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+};
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+
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+static int picoxcell_trng_probe(struct platform_device *pdev)
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+{
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+ int ret;
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+ struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+
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+ if (!mem) {
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+ dev_warn(&pdev->dev, "no memory resource\n");
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+ return -ENOMEM;
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+ }
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+
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+ if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
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+ "picoxcell_trng")) {
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+ dev_warn(&pdev->dev, "unable to request io mem\n");
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+ return -EBUSY;
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+ }
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+
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+ rng_base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
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+ if (!rng_base) {
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+ dev_warn(&pdev->dev, "unable to remap io mem\n");
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+ return -ENOMEM;
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+ }
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+
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+ rng_clk = clk_get(&pdev->dev, NULL);
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+ if (IS_ERR(rng_clk)) {
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+ dev_warn(&pdev->dev, "no clk\n");
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+ return PTR_ERR(rng_clk);
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+ }
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+
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+ ret = clk_enable(rng_clk);
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+ if (ret) {
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+ dev_warn(&pdev->dev, "unable to enable clk\n");
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+ goto err_enable;
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+ }
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+
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+ picoxcell_trng_start();
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+ ret = hwrng_register(&picoxcell_trng);
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+ if (ret)
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+ goto err_register;
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+
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+ rng_dev = &pdev->dev;
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+ dev_info(&pdev->dev, "pixoxcell random number generator active\n");
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+
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+ return 0;
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+
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+err_register:
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+ clk_disable(rng_clk);
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+err_enable:
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+ clk_put(rng_clk);
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+
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+ return ret;
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+}
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+
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+static int __devexit picoxcell_trng_remove(struct platform_device *pdev)
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+{
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+ hwrng_unregister(&picoxcell_trng);
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+ clk_disable(rng_clk);
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+ clk_put(rng_clk);
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+
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+ return 0;
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+}
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+
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+#ifdef CONFIG_PM
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+static int picoxcell_trng_suspend(struct device *dev)
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+{
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+ clk_disable(rng_clk);
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+
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+ return 0;
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+}
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+
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+static int picoxcell_trng_resume(struct device *dev)
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+{
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+ return clk_enable(rng_clk);
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+}
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+
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+static const struct dev_pm_ops picoxcell_trng_pm_ops = {
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+ .suspend = picoxcell_trng_suspend,
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+ .resume = picoxcell_trng_resume,
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+};
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+#endif /* CONFIG_PM */
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+
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+static struct platform_driver picoxcell_trng_driver = {
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+ .probe = picoxcell_trng_probe,
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+ .remove = __devexit_p(picoxcell_trng_remove),
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+ .driver = {
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+ .name = "picoxcell-trng",
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+ .owner = THIS_MODULE,
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+#ifdef CONFIG_PM
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+ .pm = &picoxcell_trng_pm_ops,
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+#endif /* CONFIG_PM */
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+ },
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+};
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+
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+static int __init picoxcell_trng_init(void)
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+{
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+ return platform_driver_register(&picoxcell_trng_driver);
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+}
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+module_init(picoxcell_trng_init);
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+
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+static void __exit picoxcell_trng_exit(void)
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+{
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+ platform_driver_unregister(&picoxcell_trng_driver);
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+}
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+module_exit(picoxcell_trng_exit);
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+
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+MODULE_LICENSE("GPL");
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+MODULE_AUTHOR("Jamie Iles");
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+MODULE_DESCRIPTION("Picochip picoXcell TRNG driver");
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