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@@ -1,9 +1,13 @@
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/*
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/*
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- * File: include/asm-blackfin/mach-bf548/anomaly.h
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- * Bugs: Enter bugs at http://blackfin.uclinux.org/
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+ * DO NOT EDIT THIS FILE
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+ * This file is under version control at
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+ * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
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+ * and can be replaced with that version at any time
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+ * DO NOT EDIT THIS FILE
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*
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*
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- * Copyright (C) 2004-2009 Analog Devices Inc.
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- * Licensed under the GPL-2 or later.
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+ * Copyright 2004-2009 Analog Devices Inc.
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+ * Licensed under the ADI BSD license.
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+ * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
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*/
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*/
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/* This file should be up to date with:
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/* This file should be up to date with:
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@@ -24,6 +28,8 @@
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#define ANOMALY_05000119 (1)
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#define ANOMALY_05000119 (1)
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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#define ANOMALY_05000122 (1)
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+/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
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+#define ANOMALY_05000220 (1)
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/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
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/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (1)
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#define ANOMALY_05000245 (1)
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/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
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/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
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@@ -200,6 +206,14 @@
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#define ANOMALY_05000466 (1)
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#define ANOMALY_05000466 (1)
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/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
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/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
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#define ANOMALY_05000467 (1)
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#define ANOMALY_05000467 (1)
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+/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
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+#define ANOMALY_05000473 (1)
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+/* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */
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+#define ANOMALY_05000474 (1)
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+/* Core Hang With L2/L3 Configured in Writeback Cache Mode */
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+#define ANOMALY_05000475 (1)
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+/* TESTSET Instruction Cannot Be Interrupted */
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+#define ANOMALY_05000477 (1)
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/* Anomalies that don't exist on this proc */
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000099 (0)
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#define ANOMALY_05000099 (0)
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@@ -215,7 +229,6 @@
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#define ANOMALY_05000198 (0)
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#define ANOMALY_05000198 (0)
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#define ANOMALY_05000202 (0)
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#define ANOMALY_05000202 (0)
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#define ANOMALY_05000215 (0)
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#define ANOMALY_05000215 (0)
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-#define ANOMALY_05000220 (0)
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#define ANOMALY_05000227 (0)
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#define ANOMALY_05000227 (0)
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#define ANOMALY_05000230 (0)
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#define ANOMALY_05000230 (0)
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#define ANOMALY_05000231 (0)
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#define ANOMALY_05000231 (0)
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