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@@ -2657,6 +2657,7 @@ static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
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struct rt2x00_field32 field;
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int retval;
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u32 reg;
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+ u32 offset;
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/*
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* First pass the configuration through rt2x00lib, that will
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@@ -2668,24 +2669,23 @@ static int rt61pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
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if (retval)
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return retval;
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+ /*
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+ * We only need to perform additional register initialization
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+ * for WMM queues/
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+ */
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+ if (queue_idx >= 4)
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+ return 0;
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+
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queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
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/* Update WMM TXOP register */
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- if (queue_idx < 2) {
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- field.bit_offset = queue_idx * 16;
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- field.bit_mask = 0xffff << field.bit_offset;
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-
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- rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, ®);
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- rt2x00_set_field32(®, field, queue->txop);
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- rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
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- } else if (queue_idx < 4) {
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- field.bit_offset = (queue_idx - 2) * 16;
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- field.bit_mask = 0xffff << field.bit_offset;
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-
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- rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, ®);
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- rt2x00_set_field32(®, field, queue->txop);
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- rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
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- }
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+ offset = AC_TXOP_CSR0 + (sizeof(u32) * (!!(queue_idx & 2)));
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+ field.bit_offset = (queue_idx & 1) * 16;
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+ field.bit_mask = 0xffff << field.bit_offset;
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+
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+ rt2x00pci_register_read(rt2x00dev, offset, ®);
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+ rt2x00_set_field32(®, field, queue->txop);
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+ rt2x00pci_register_write(rt2x00dev, offset, reg);
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/* Update WMM registers */
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field.bit_offset = queue_idx * 4;
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