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+/*
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+ * linux/drivers/mfd/mcp-sa11x0.c
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+ *
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+ * Copyright (C) 2001-2005 Russell King
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License.
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+ *
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+ * SA11x0 MCP (Multimedia Communications Port) driver.
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+ *
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+ * MCP read/write timeouts from Jordi Colomer, rehacked by rmk.
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+ */
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+#include <linux/module.h>
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+#include <linux/init.h>
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+#include <linux/errno.h>
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+#include <linux/kernel.h>
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+#include <linux/delay.h>
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+#include <linux/spinlock.h>
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+#include <linux/slab.h>
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+#include <linux/device.h>
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+
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+#include <asm/dma.h>
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+#include <asm/hardware.h>
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+#include <asm/mach-types.h>
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+#include <asm/system.h>
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+
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+#include <asm/arch/assabet.h>
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+
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+#include "mcp.h"
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+
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+struct mcp_sa11x0 {
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+ u32 mccr0;
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+ u32 mccr1;
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+};
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+
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+#define priv(mcp) ((struct mcp_sa11x0 *)mcp_priv(mcp))
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+
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+static void
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+mcp_sa11x0_set_telecom_divisor(struct mcp *mcp, unsigned int divisor)
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+{
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+ unsigned int mccr0;
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+
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+ divisor /= 32;
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+
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+ mccr0 = Ser4MCCR0 & ~0x00007f00;
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+ mccr0 |= divisor << 8;
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+ Ser4MCCR0 = mccr0;
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+}
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+
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+static void
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+mcp_sa11x0_set_audio_divisor(struct mcp *mcp, unsigned int divisor)
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+{
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+ unsigned int mccr0;
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+
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+ divisor /= 32;
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+
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+ mccr0 = Ser4MCCR0 & ~0x0000007f;
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+ mccr0 |= divisor;
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+ Ser4MCCR0 = mccr0;
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+}
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+
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+/*
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+ * Write data to the device. The bit should be set after 3 subframe
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+ * times (each frame is 64 clocks). We wait a maximum of 6 subframes.
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+ * We really should try doing something more productive while we
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+ * wait.
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+ */
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+static void
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+mcp_sa11x0_write(struct mcp *mcp, unsigned int reg, unsigned int val)
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+{
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+ int ret = -ETIME;
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+ int i;
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+
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+ Ser4MCDR2 = reg << 17 | MCDR2_Wr | (val & 0xffff);
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+
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+ for (i = 0; i < 2; i++) {
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+ udelay(mcp->rw_timeout);
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+ if (Ser4MCSR & MCSR_CWC) {
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+ ret = 0;
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+ break;
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+ }
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+ }
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+
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+ if (ret < 0)
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+ printk(KERN_WARNING "mcp: write timed out\n");
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+}
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+
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+/*
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+ * Read data from the device. The bit should be set after 3 subframe
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+ * times (each frame is 64 clocks). We wait a maximum of 6 subframes.
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+ * We really should try doing something more productive while we
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+ * wait.
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+ */
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+static unsigned int
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+mcp_sa11x0_read(struct mcp *mcp, unsigned int reg)
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+{
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+ int ret = -ETIME;
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+ int i;
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+
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+ Ser4MCDR2 = reg << 17 | MCDR2_Rd;
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+
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+ for (i = 0; i < 2; i++) {
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+ udelay(mcp->rw_timeout);
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+ if (Ser4MCSR & MCSR_CRC) {
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+ ret = Ser4MCDR2 & 0xffff;
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+ break;
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+ }
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+ }
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+
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+ if (ret < 0)
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+ printk(KERN_WARNING "mcp: read timed out\n");
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+
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+ return ret;
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+}
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+
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+static void mcp_sa11x0_enable(struct mcp *mcp)
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+{
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+ Ser4MCSR = -1;
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+ Ser4MCCR0 |= MCCR0_MCE;
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+}
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+
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+static void mcp_sa11x0_disable(struct mcp *mcp)
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+{
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+ Ser4MCCR0 &= ~MCCR0_MCE;
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+}
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+
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+/*
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+ * Our methods.
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+ */
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+static struct mcp_ops mcp_sa11x0 = {
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+ .set_telecom_divisor = mcp_sa11x0_set_telecom_divisor,
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+ .set_audio_divisor = mcp_sa11x0_set_audio_divisor,
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+ .reg_write = mcp_sa11x0_write,
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+ .reg_read = mcp_sa11x0_read,
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+ .enable = mcp_sa11x0_enable,
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+ .disable = mcp_sa11x0_disable,
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+};
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+
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+static int mcp_sa11x0_probe(struct device *dev)
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+{
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+ struct platform_device *pdev = to_platform_device(dev);
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+ struct mcp *mcp;
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+ int ret;
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+
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+ if (!machine_is_adsbitsy() && !machine_is_assabet() &&
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+ !machine_is_cerf() && !machine_is_flexanet() &&
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+ !machine_is_freebird() && !machine_is_graphicsclient() &&
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+ !machine_is_graphicsmaster() && !machine_is_lart() &&
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+ !machine_is_omnimeter() && !machine_is_pfs168() &&
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+ !machine_is_shannon() && !machine_is_simpad() &&
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+ !machine_is_yopy())
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+ return -ENODEV;
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+
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+ if (!request_mem_region(0x80060000, 0x60, "sa11x0-mcp"))
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+ return -EBUSY;
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+
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+ mcp = mcp_host_alloc(&pdev->dev, sizeof(struct mcp_sa11x0));
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+ if (!mcp) {
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+ ret = -ENOMEM;
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+ goto release;
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+ }
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+
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+ mcp->owner = THIS_MODULE;
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+ mcp->ops = &mcp_sa11x0;
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+ mcp->sclk_rate = 11981000,
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+ mcp->dma_audio_rd = DMA_Ser4MCP0Rd;
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+ mcp->dma_audio_wr = DMA_Ser4MCP0Wr;
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+ mcp->dma_telco_rd = DMA_Ser4MCP1Rd;
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+ mcp->dma_telco_wr = DMA_Ser4MCP1Wr;
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+
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+ dev_set_drvdata(dev, mcp);
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+
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+ if (machine_is_assabet()) {
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+ ASSABET_BCR_set(ASSABET_BCR_CODEC_RST);
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+ }
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+
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+ /*
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+ * Setup the PPC unit correctly.
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+ */
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+ PPDR &= ~PPC_RXD4;
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+ PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
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+ PSDR |= PPC_RXD4;
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+ PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
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+ PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
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+
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+ Ser4MCSR = -1;
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+ Ser4MCCR1 = 0;
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+ Ser4MCCR0 = 0x00007f7f | MCCR0_ADM;
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+
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+ /*
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+ * Calculate the read/write timeout (us) from the bit clock
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+ * rate. This is the period for 3 64-bit frames. Always
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+ * round this time up.
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+ */
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+ mcp->rw_timeout = (64 * 3 * 1000000 + mcp->sclk_rate - 1) /
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+ mcp->sclk_rate;
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+
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+ ret = mcp_host_register(mcp);
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+ if (ret == 0)
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+ goto out;
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+
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+ release:
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+ release_mem_region(0x80060000, 0x60);
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+ dev_set_drvdata(dev, NULL);
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+
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+ out:
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+ return ret;
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+}
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+
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+static int mcp_sa11x0_remove(struct device *dev)
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+{
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+ struct mcp *mcp = dev_get_drvdata(dev);
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+
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+ dev_set_drvdata(dev, NULL);
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+ mcp_host_unregister(mcp);
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+ release_mem_region(0x80060000, 0x60);
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+
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+ return 0;
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+}
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+
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+static int mcp_sa11x0_suspend(struct device *dev, pm_message_t state, u32 level)
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+{
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+ struct mcp *mcp = dev_get_drvdata(dev);
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+
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+ if (level == SUSPEND_DISABLE) {
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+ priv(mcp)->mccr0 = Ser4MCCR0;
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+ priv(mcp)->mccr1 = Ser4MCCR1;
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+ Ser4MCCR0 &= ~MCCR0_MCE;
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+ }
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+ return 0;
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+}
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+
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+static int mcp_sa11x0_resume(struct device *dev, u32 level)
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+{
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+ struct mcp *mcp = dev_get_drvdata(dev);
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+
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+ if (level == RESUME_RESTORE_STATE) {
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+ Ser4MCCR1 = priv(mcp)->mccr1;
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+ Ser4MCCR0 = priv(mcp)->mccr0;
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+ }
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+ return 0;
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+}
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+
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+/*
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+ * The driver for the SA11x0 MCP port.
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+ */
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+static struct device_driver mcp_sa11x0_driver = {
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+ .name = "sa11x0-mcp",
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+ .bus = &platform_bus_type,
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+ .probe = mcp_sa11x0_probe,
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+ .remove = mcp_sa11x0_remove,
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+ .suspend = mcp_sa11x0_suspend,
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+ .resume = mcp_sa11x0_resume,
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+};
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+
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+/*
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+ * This needs re-working
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+ */
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+static int __init mcp_sa11x0_init(void)
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+{
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+ return driver_register(&mcp_sa11x0_driver);
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+}
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+
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+static void __exit mcp_sa11x0_exit(void)
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+{
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+ driver_unregister(&mcp_sa11x0_driver);
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+}
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+
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+module_init(mcp_sa11x0_init);
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+module_exit(mcp_sa11x0_exit);
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+
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+MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
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+MODULE_DESCRIPTION("SA11x0 multimedia communications port driver");
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+MODULE_LICENSE("GPL");
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