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@@ -223,7 +223,7 @@ static void cmd64x_set_dma_mode(ide_drive_t *drive, const u8 speed)
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(void) pci_write_config_byte(dev, pciU, regU);
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}
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-static int cmd648_ide_dma_end (ide_drive_t *drive)
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+static int cmd648_dma_end(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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unsigned long base = hwif->dma_base - (hwif->channel * 8);
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@@ -239,7 +239,7 @@ static int cmd648_ide_dma_end (ide_drive_t *drive)
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return err;
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}
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-static int cmd64x_ide_dma_end (ide_drive_t *drive)
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+static int cmd64x_dma_end(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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@@ -256,7 +256,7 @@ static int cmd64x_ide_dma_end (ide_drive_t *drive)
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return err;
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}
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-static int cmd648_ide_dma_test_irq (ide_drive_t *drive)
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+static int cmd648_dma_test_irq(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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unsigned long base = hwif->dma_base - (hwif->channel * 8);
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@@ -279,7 +279,7 @@ static int cmd648_ide_dma_test_irq (ide_drive_t *drive)
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return 0;
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}
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-static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
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+static int cmd64x_dma_test_irq(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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@@ -310,7 +310,7 @@ static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
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* event order for DMA transfers.
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*/
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-static int cmd646_1_ide_dma_end (ide_drive_t *drive)
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+static int cmd646_1_dma_end(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = HWIF(drive);
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u8 dma_stat = 0, dma_cmd = 0;
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@@ -385,62 +385,33 @@ static u8 __devinit cmd64x_cable_detect(ide_hwif_t *hwif)
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}
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}
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-static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
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-{
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- struct pci_dev *dev = to_pci_dev(hwif->dev);
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-
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- if (!hwif->dma_base)
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- return;
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-
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- /*
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- * UltraDMA only supported on PCI646U and PCI646U2, which
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- * correspond to revisions 0x03, 0x05 and 0x07 respectively.
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- * Actually, although the CMD tech support people won't
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- * tell me the details, the 0x03 revision cannot support
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- * UDMA correctly without hardware modifications, and even
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- * then it only works with Quantum disks due to some
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- * hold time assumptions in the 646U part which are fixed
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- * in the 646U2.
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- *
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- * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
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- */
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- if (dev->device == PCI_DEVICE_ID_CMD_646 && dev->revision < 5)
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- hwif->ultra_mask = 0x00;
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-
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- switch (dev->device) {
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- case PCI_DEVICE_ID_CMD_648:
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- case PCI_DEVICE_ID_CMD_649:
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- alt_irq_bits:
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- hwif->ide_dma_end = &cmd648_ide_dma_end;
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- hwif->ide_dma_test_irq = &cmd648_ide_dma_test_irq;
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- break;
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- case PCI_DEVICE_ID_CMD_646:
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- if (dev->revision == 0x01) {
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- hwif->ide_dma_end = &cmd646_1_ide_dma_end;
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- break;
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- } else if (dev->revision >= 0x03)
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- goto alt_irq_bits;
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- /* fall thru */
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- default:
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- hwif->ide_dma_end = &cmd64x_ide_dma_end;
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- hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
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- break;
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- }
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-}
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-
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static const struct ide_port_ops cmd64x_port_ops = {
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.set_pio_mode = cmd64x_set_pio_mode,
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.set_dma_mode = cmd64x_set_dma_mode,
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.cable_detect = cmd64x_cable_detect,
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};
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+static struct ide_dma_ops cmd64x_dma_ops = {
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+ .dma_end = cmd64x_dma_end,
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+ .dma_test_irq = cmd64x_dma_test_irq,
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+};
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+
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+static struct ide_dma_ops cmd646_rev1_dma_ops = {
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+ .dma_end = cmd646_1_dma_end,
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+};
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+
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+static struct ide_dma_ops cmd648_dma_ops = {
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+ .dma_end = cmd648_dma_end,
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+ .dma_test_irq = cmd648_dma_test_irq,
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+};
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+
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static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
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{ /* 0 */
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.name = "CMD643",
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.init_chipset = init_chipset_cmd64x,
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- .init_hwif = init_hwif_cmd64x,
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.enablebits = {{0x00,0x00,0x00}, {0x51,0x08,0x08}},
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.port_ops = &cmd64x_port_ops,
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+ .dma_ops = &cmd64x_dma_ops,
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.host_flags = IDE_HFLAG_CLEAR_SIMPLEX |
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IDE_HFLAG_ABUSE_PREFETCH,
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.pio_mask = ATA_PIO5,
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@@ -449,10 +420,10 @@ static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
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},{ /* 1 */
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.name = "CMD646",
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.init_chipset = init_chipset_cmd64x,
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- .init_hwif = init_hwif_cmd64x,
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.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
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.chipset = ide_cmd646,
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.port_ops = &cmd64x_port_ops,
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+ .dma_ops = &cmd648_dma_ops,
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.host_flags = IDE_HFLAG_ABUSE_PREFETCH,
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.pio_mask = ATA_PIO5,
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.mwdma_mask = ATA_MWDMA2,
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@@ -460,9 +431,9 @@ static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
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},{ /* 2 */
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.name = "CMD648",
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.init_chipset = init_chipset_cmd64x,
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- .init_hwif = init_hwif_cmd64x,
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.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
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.port_ops = &cmd64x_port_ops,
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+ .dma_ops = &cmd648_dma_ops,
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.host_flags = IDE_HFLAG_ABUSE_PREFETCH,
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.pio_mask = ATA_PIO5,
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.mwdma_mask = ATA_MWDMA2,
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@@ -470,9 +441,9 @@ static const struct ide_port_info cmd64x_chipsets[] __devinitdata = {
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},{ /* 3 */
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.name = "CMD649",
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.init_chipset = init_chipset_cmd64x,
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- .init_hwif = init_hwif_cmd64x,
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.enablebits = {{0x51,0x04,0x04}, {0x51,0x08,0x08}},
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.port_ops = &cmd64x_port_ops,
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+ .dma_ops = &cmd648_dma_ops,
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.host_flags = IDE_HFLAG_ABUSE_PREFETCH,
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.pio_mask = ATA_PIO5,
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.mwdma_mask = ATA_MWDMA2,
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@@ -487,12 +458,35 @@ static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_devic
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d = cmd64x_chipsets[idx];
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- /*
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- * The original PCI0646 didn't have the primary channel enable bit,
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- * it appeared starting with PCI0646U (i.e. revision ID 3).
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- */
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- if (idx == 1 && dev->revision < 3)
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- d.enablebits[0].reg = 0;
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+ if (idx == 1) {
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+ /*
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+ * UltraDMA only supported on PCI646U and PCI646U2, which
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+ * correspond to revisions 0x03, 0x05 and 0x07 respectively.
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+ * Actually, although the CMD tech support people won't
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+ * tell me the details, the 0x03 revision cannot support
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+ * UDMA correctly without hardware modifications, and even
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+ * then it only works with Quantum disks due to some
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+ * hold time assumptions in the 646U part which are fixed
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+ * in the 646U2.
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+ *
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+ * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
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+ */
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+ if (dev->revision < 5) {
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+ d.udma_mask = 0x00;
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+ /*
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+ * The original PCI0646 didn't have the primary
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+ * channel enable bit, it appeared starting with
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+ * PCI0646U (i.e. revision ID 3).
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+ */
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+ if (dev->revision < 3) {
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+ d.enablebits[0].reg = 0;
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+ if (dev->revision == 1)
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+ d.dma_ops = &cmd646_rev1_dma_ops;
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+ else
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+ d.dma_ops = &cmd64x_dma_ops;
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+ }
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+ }
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+ }
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return ide_setup_pci_device(dev, &d);
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}
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