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@@ -967,7 +967,7 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
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intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
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}
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- if (is_cpu_edp(intel_dp))
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+ if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
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ironlake_set_pll_edp(crtc, adjusted_mode->clock);
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}
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@@ -1331,7 +1331,7 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
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if (!(tmp & DP_PORT_EN))
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return false;
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- if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
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+ if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
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*pipe = PORT_TO_PIPE_CPT(tmp);
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} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
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*pipe = PORT_TO_PIPE(tmp);
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