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@@ -156,19 +156,19 @@ bit 0 (V4L2_DV_VSYNC_POS_POL) is for vertical sync polarity and bit 1 (V4L2_DV_H
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<entry>__u32</entry>
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<entry><structfield>il_vfrontporch</structfield></entry>
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<entry>Vertical front porch in lines for the even field (aka field 2) of
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- interlaced field formats.</entry>
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+ interlaced field formats. Must be 0 for progressive formats.</entry>
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</row>
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<row>
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<entry>__u32</entry>
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<entry><structfield>il_vsync</structfield></entry>
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<entry>Vertical sync length in lines for the even field (aka field 2) of
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- interlaced field formats.</entry>
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+ interlaced field formats. Must be 0 for progressive formats.</entry>
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</row>
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<row>
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<entry>__u32</entry>
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<entry><structfield>il_vbackporch</structfield></entry>
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<entry>Vertical back porch in lines for the even field (aka field 2) of
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- interlaced field formats.</entry>
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+ interlaced field formats. Must be 0 for progressive formats.</entry>
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</row>
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<row>
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<entry>__u32</entry>
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