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@@ -34,92 +34,6 @@
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static struct otg_transceiver *otg;
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-/*
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- * ehci_run defined in drivers/usb/host/ehci-hcd.c reset the controller and
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- * the configuration settings in ehci_msm_reset vanish after controller is
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- * reset. Resetting the controler in ehci_run seems to be un-necessary
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- * provided HCD reset the controller before calling ehci_run. Most of the HCD
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- * do but some are not. So this function is same as ehci_run but we don't
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- * reset the controller here.
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- */
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-static int ehci_msm_run(struct usb_hcd *hcd)
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-{
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- struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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- u32 temp;
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- u32 hcc_params;
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-
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- hcd->uses_new_polling = 1;
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-
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- ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list);
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- ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next);
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-
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- /*
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- * hcc_params controls whether ehci->regs->segment must (!!!)
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- * be used; it constrains QH/ITD/SITD and QTD locations.
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- * pci_pool consistent memory always uses segment zero.
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- * streaming mappings for I/O buffers, like pci_map_single(),
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- * can return segments above 4GB, if the device allows.
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- *
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- * NOTE: the dma mask is visible through dma_supported(), so
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- * drivers can pass this info along ... like NETIF_F_HIGHDMA,
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- * Scsi_Host.highmem_io, and so forth. It's readonly to all
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- * host side drivers though.
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- */
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- hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params);
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- if (HCC_64BIT_ADDR(hcc_params))
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- ehci_writel(ehci, 0, &ehci->regs->segment);
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-
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- /*
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- * Philips, Intel, and maybe others need CMD_RUN before the
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- * root hub will detect new devices (why?); NEC doesn't
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- */
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- ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
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- ehci->command |= CMD_RUN;
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- ehci_writel(ehci, ehci->command, &ehci->regs->command);
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- dbg_cmd(ehci, "init", ehci->command);
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-
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- /*
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- * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
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- * are explicitly handed to companion controller(s), so no TT is
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- * involved with the root hub. (Except where one is integrated,
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- * and there's no companion controller unless maybe for USB OTG.)
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- *
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- * Turning on the CF flag will transfer ownership of all ports
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- * from the companions to the EHCI controller. If any of the
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- * companions are in the middle of a port reset at the time, it
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- * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
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- * guarantees that no resets are in progress. After we set CF,
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- * a short delay lets the hardware catch up; new resets shouldn't
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- * be started before the port switching actions could complete.
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- */
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- down_write(&ehci_cf_port_reset_rwsem);
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- hcd->state = HC_STATE_RUNNING;
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- ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag);
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- ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */
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- usleep_range(5000, 5500);
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- up_write(&ehci_cf_port_reset_rwsem);
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- ehci->last_periodic_enable = ktime_get_real();
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-
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- temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
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- ehci_info(ehci,
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- "USB %x.%x started, EHCI %x.%02x%s\n",
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- ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
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- temp >> 8, temp & 0xff,
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- ignore_oc ? ", overcurrent ignored" : "");
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-
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- ehci_writel(ehci, INTR_MASK,
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- &ehci->regs->intr_enable); /* Turn On Interrupts */
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-
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- /* GRR this is run-once init(), being done every time the HC starts.
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- * So long as they're part of class devices, we can't do it init()
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- * since the class device isn't created that early.
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- */
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- create_debug_files(ehci);
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- create_companion_file(ehci);
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-
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- return 0;
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-}
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-
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static int ehci_msm_reset(struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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@@ -135,6 +49,10 @@ static int ehci_msm_reset(struct usb_hcd *hcd)
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hcd->has_tt = 1;
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ehci->sbrn = HCD_USB2;
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+ retval = ehci_halt(ehci);
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+ if (retval)
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+ return retval;
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+
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/* data structure init */
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retval = ehci_init(hcd);
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if (retval)
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@@ -167,7 +85,7 @@ static struct hc_driver msm_hc_driver = {
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.flags = HCD_USB2 | HCD_MEMORY,
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.reset = ehci_msm_reset,
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- .start = ehci_msm_run,
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+ .start = ehci_run,
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.stop = ehci_stop,
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.shutdown = ehci_shutdown,
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