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MIPS: Octeon: Workaround link failures with gcc-4.4.x 32-bits toolchains

When building with a gcc-4.4.x toolchain that is configured to produce
32-bits executables by default, we will produce __lshrti3 in sched_clock()
which is never resolved so the kernel fails to link. Unconditionally use
the inline assembly version as suggested by David Daney, which works around
the issue.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/1514/
Acked-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Florian Fainelli 15 years ago
parent
commit
5c8974538a
1 changed files with 0 additions and 8 deletions
  1. 0 8
      arch/mips/cavium-octeon/csrc-octeon.c

+ 0 - 8
arch/mips/cavium-octeon/csrc-octeon.c

@@ -53,7 +53,6 @@ static struct clocksource clocksource_mips = {
 unsigned long long notrace sched_clock(void)
 {
 	/* 64-bit arithmatic can overflow, so use 128-bit.  */
-#if (__GNUC__ < 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ <= 3))
 	u64 t1, t2, t3;
 	unsigned long long rv;
 	u64 mult = clocksource_mips.mult;
@@ -73,13 +72,6 @@ unsigned long long notrace sched_clock(void)
 		: [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift)
 		: "hi", "lo");
 	return rv;
-#else
-	/* GCC > 4.3 do it the easy way.  */
-	unsigned int __attribute__((mode(TI))) t;
-	t = read_c0_cvmcount();
-	t = t * clocksource_mips.mult;
-	return (unsigned long long)(t >> clocksource_mips.shift);
-#endif
 }
 
 void __init plat_time_init(void)