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@@ -0,0 +1,40 @@
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+#ifndef _SPARC_ASM_H
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+#define _SPARC_ASM_H
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+
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+/* Macros to assist the sharing of assembler code between 32-bit and
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+ * 64-bit sparc.
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+ */
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+
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+#ifdef CONFIG_SPARC64
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+#define BRANCH32(TYPE, PREDICT, DEST) \
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+ TYPE,PREDICT %icc, DEST
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+#define BRANCH32_ANNUL(TYPE, PREDICT, DEST) \
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+ TYPE,a,PREDICT %icc, DEST
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+#define BRANCH_REG_ZERO(PREDICT, REG, DEST) \
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+ brz,PREDICT REG, DEST
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+#define BRANCH_REG_ZERO_ANNUL(PREDICT, REG, DEST) \
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+ brz,a,PREDICT REG, DEST
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+#define BRANCH_REG_NOT_ZERO(PREDICT, REG, DEST) \
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+ brnz,PREDICT REG, DEST
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+#define BRANCH_REG_NOT_ZERO_ANNUL(PREDICT, REG, DEST) \
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+ brnz,a,PREDICT REG, DEST
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+#else
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+#define BRANCH32(TYPE, PREDICT, DEST) \
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+ TYPE DEST
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+#define BRANCH32_ANNUL(TYPE, PREDICT, DEST) \
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+ TYPE,a DEST
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+#define BRANCH_REG_ZERO(PREDICT, REG, DEST) \
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+ cmp REG, 0; \
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+ be DEST
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+#define BRANCH_REG_ZERO_ANNUL(PREDICT, REG, DEST) \
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+ cmp REG, 0; \
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+ be,a DEST
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+#define BRANCH_REG_NOT_ZERO(PREDICT, REG, DEST) \
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+ cmp REG, 0; \
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+ bne DEST
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+#define BRANCH_REG_NOT_ZERO_ANNUL(PREDICT, REG, DEST) \
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+ cmp REG, 0; \
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+ bne,a DEST
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+#endif
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+
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+#endif /* _SPARC_ASM_H */
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