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@@ -826,8 +826,6 @@ static void amd64_dump_dramcfg_low(u32 dclr, int chan)
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/* Display and decode various NB registers for debug purposes. */
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static void amd64_dump_misc_regs(struct amd64_pvt *pvt)
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{
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- int ganged;
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-
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debugf1("F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);
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debugf1(" NB two channel DRAM capable: %s\n",
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@@ -851,28 +849,19 @@ static void amd64_dump_misc_regs(struct amd64_pvt *pvt)
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debugf1(" DramHoleValid: %s\n",
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(pvt->dhar & DHAR_VALID) ? "yes" : "no");
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+ amd64_debug_display_dimm_sizes(0, pvt);
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+
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/* everything below this point is Fam10h and above */
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- if (boot_cpu_data.x86 == 0xf) {
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- amd64_debug_display_dimm_sizes(0, pvt);
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+ if (boot_cpu_data.x86 == 0xf)
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return;
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- }
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+
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+ amd64_debug_display_dimm_sizes(1, pvt);
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amd64_info("using %s syndromes.\n", ((pvt->syn_type == 8) ? "x8" : "x4"));
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/* Only if NOT ganged does dclr1 have valid info */
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if (!dct_ganging_enabled(pvt))
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amd64_dump_dramcfg_low(pvt->dclr1, 1);
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-
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- /*
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- * Determine if ganged and then dump memory sizes for first controller,
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- * and if NOT ganged dump info for 2nd controller.
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- */
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- ganged = dct_ganging_enabled(pvt);
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-
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- amd64_debug_display_dimm_sizes(0, pvt);
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-
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- if (!ganged)
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- amd64_debug_display_dimm_sizes(1, pvt);
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}
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/* Read in both of DBAM registers */
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@@ -1644,11 +1633,10 @@ static void amd64_debug_display_dimm_sizes(int ctrl, struct amd64_pvt *pvt)
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WARN_ON(ctrl != 0);
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}
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- debugf1("F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n",
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- ctrl, ctrl ? pvt->dbam1 : pvt->dbam0);
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+ dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1 : pvt->dbam0;
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+ dcsb = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dcsb1 : pvt->dcsb0;
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- dbam = ctrl ? pvt->dbam1 : pvt->dbam0;
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- dcsb = ctrl ? pvt->dcsb1 : pvt->dcsb0;
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+ debugf1("F2x%d80 (DRAM Bank Address Mapping): 0x%08x\n", ctrl, dbam);
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edac_printk(KERN_DEBUG, EDAC_MC, "DCT%d chip selects:\n", ctrl);
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